Watchdog reset circuit for serial counting and working method
A reset circuit and watchdog technology, applied in data reset devices, counting mechanisms/items, calculations, etc., can solve problems such as unfavorable counting cycle expansion, and achieve the effect of saving circuit area and optimizing circuit area.
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Embodiment 1
[0028] The present invention provides a serial counting watchdog reset circuit, its structure is as follows figure 1 As shown, it includes a reference module, a voltage sampling module, a comparator, a clock module, a watchdog counting module, a logic control module, and an output module. The voltage sampling module and the reference module are respectively connected to the same direction and reverse input terminals of the comparator A0; the first input terminal IN0 of the logic control module is connected to the output terminal of the comparator, and the second input terminal IN0 is connected to the output terminal of the comparator. The terminal IN1 is connected to the input signal in, and the third input terminal IN2 is connected to the output terminal of the watchdog counting module; the first output terminal out0 of the logic control module is connected to the input terminal of the output module; the second output terminal out1 is connected to The input terminal of the cl...
Embodiment 2
[0039] The present invention also provides a working method of a serial counting watchdog reset circuit, the process of which is as follows: image 3 shown, including the following steps:
[0040] Step 1. The circuit is powered on and started. When the voltage VCC meets the design requirements, the overall circuit starts to work normally after power-on reset. When the power is turned on, the first watchdog counting cycle WT1 is T1·T2·T3·T4·T5;
[0041] Step 2. After power-on reset, the watchdog counting module starts counting, and the first watchdog counting period is WT1;
[0042] Step 3. When the count reaches WT1, the circuit enters normal counting, and the counting period is switched to WT2;
[0043] Step 4. When the circuit is working normally, the voltage VCC has an abnormal disturbance. When the disturbance makes VCC not meet the design requirements, the degree of VCC disturbance determines the logic signal of A0 and A1. Set WT1 through A0 and A1. After the disturbance...
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