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A crc16-based single-bit error correction fpga implementation method

A technology of CRC16 and an implementation method, applied in the computer field, can solve the problems of large resource consumption, waste of resources, low efficiency, etc., and achieve the effects of high data processing efficiency, reducing data bit width, and reducing address space.

Active Publication Date: 2022-04-12
SHANDONG INST OF COMMERCE & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] Existing technical schemes are divided into two kinds of realization in CPU (central processing unit) and realization in FPGA, and CPU can't realize the parallel processing of data, and efficiency is low, and the realization scheme of FPGA usually combines data information and redundancy at the receiving end. Separate processing of inspection information increases the delay and reduces the efficiency of data processing. In the process of looking up the table, the calculated CRC value is used as the retrieval address of RAM (Random Access Memory). Since the data bit width is relatively large, so Occupies too many on-chip RAM and logic resources of the FPGA, resulting in a waste of resources
This existing solution is inefficient and consumes a lot of resources

Method used

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  • A crc16-based single-bit error correction fpga implementation method
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  • A crc16-based single-bit error correction fpga implementation method

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Embodiment Construction

[0031] In order to clearly illustrate the technical features of the solution of the present invention, the solution will be further elaborated below in conjunction with the accompanying drawings and through specific implementation methods.

[0032] The calculation value of the check code at the receiving end is only related to the transmission error and the generator polynomial, and has nothing to do with the transmitted information data. Regarding the above conclusions, a brief explanation is given by taking the production polynomial of CRC-16 as x16+x12+x5+1, as shown in Table 1.

[0033] Table 1 CRC value corresponding to a single bit error

[0034]

[0035]

[0036] In this example, if figure 2 and image 3 As shown in , it is a single-bit error correction FPGA implementation method based on CRC16, including a data cache module, a read cache control module, an error judgment arbitration module and a transmission control module, wherein the error judgment arbitrati...

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Abstract

The present invention relates to a single-bit error correction FPGA implementation method based on CRC16, comprising a data cache module, a read cache control module, an error judgment arbitration module and a transmission control module, and the error judgment arbitration module includes a CRC calculation module, a Hash mapping module and The error query judgment module, the present invention sends the data information and the redundant information together into the CRC calculation module for Hash operation, which reduces the delay in the data processing and judgment process, reduces the data bit width, that is, reduces the address space for data retrieval , which has the beneficial effects of high data processing efficiency and saving hardware resources.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to data transmission processing technology, in particular to a single-bit error correction FPGA implementation method based on CRC16. Background technique [0002] In today's era of big data, higher requirements are put forward for the security and efficiency of data transmission. The main point in security is the correctness of data transmission. Transmission efficiency refers to occupying less bandwidth while transmitting the same data, that is, transmitting more data with a certain bandwidth. If the data transmission is wrong, the data needs to be retransmitted, which takes up extra bandwidth and reduces the transmission efficiency. Today, with the popularity of electronic equipment, electromagnetic interference exists everywhere, which has caused great disadvantages to the security of data transmission, and at the same time puts forward higher requirements for data t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05B19/042
CPCG05B19/0423G05B2219/25257
Inventor 王秀翠朱佳侯磊孟繁兴张义王立英
Owner SHANDONG INST OF COMMERCE & TECH
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