Single-bit error correction FPGA implementation method based on CRC16

Abstract

The invention relates to a single-bit error correction FPGA (Field Programmable Gate Array) implementation method based on CRC16 (Cyclic Redundancy Check 16). The method comprises a data cache module, a read cache control module, an error judgment arbitration module and a sending control module, and the error judgment arbitration module comprises a CRC (Cyclic Redundancy Check) calculation module, a Hash mapping module and an error query judgment module. According to the method, the data information and the redundant information are sent into the CRC calculation module together for Hash operation, delay in the data processing and judging process is reduced, the data bit width is reduced, in other words, the address space of data retrieval is reduced, and the method has the beneficial effects of being high in data processing efficiency and saving hardware resources.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to data transmission processing technology, in particular to a single-bit error correction FPGA implementation method based on CRC16. Background technique [0002] In today's era of big data, higher requirements are put forward for the security and efficiency of data transmission. The main point in security is the correctness of data transmission. Transmission efficiency refers to occupying less bandwidth while transmitting the same data, that is, transmitting more data with a certain bandwidth. If the data transmission is wrong, the data needs to be retransmitted, which takes up extra bandwidth and reduces the transmission efficiency. Today, with the popularity of electronic equipment, electromagnetic interference exists everywhere, which has caused great disadvantages to the security of data transmission, and at the same time puts forward higher requirements for data t...

AI Technical Summary

Problems solved by technology

[0008] Existing technical schemes are divided into two kinds of realization in CPU (central processing unit) and realization in FPGA, and CPU can't realize the parallel processing of data, and efficiency is low, and the realization scheme of FPGA usually combines data information and redundancy at the receiving end. Separate processing of inspection information increases the delay and reduces the efficiency of data processing. In the process of looking up the table, the calculated CRC value is used as the retrieval address of RAM (Random Access Memory). Since the data bit width is relatively large, so Occupies too many on-chip RAM and logic resources of the FPGA, resulting in a waste of resources

This existing solution is inefficient and consumes a lot of resources

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