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10-gigabit communication data parallel analysis method and device based on quick protocol

A technology of communication data and analysis method, which is applied in the field of parallel analysis devices for 10 Gigabit communication data, and can solve the problems of wasting storage resources and the like

Pending Publication Date: 2021-11-23
EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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  • Application Information

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Problems solved by technology

and waste huge storage resources

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  • 10-gigabit communication data parallel analysis method and device based on quick protocol
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  • 10-gigabit communication data parallel analysis method and device based on quick protocol

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Embodiment Construction

[0032] Such as Figure 4 As shown, this parallel analysis method of 10 Gigabit communication data based on the FAST protocol uses an FPGA processing chip to build a hardware parallel processing system, which includes the following steps:

[0033] (1) start;

[0034] (2) Data reception: 16 bytes of data are received at a frequency of 156.25MHz;

[0035] (3) Parallel data decoding, output at a frequency of 156.25M Hz in parallel pipeline operation;

[0036] (4) Data allocation is performed according to the position of the bitmap in the FAST protocol;

[0037] (5) END.

[0038] The present invention builds a hardware parallel processing system with an FPGA processing chip, receives 16 bytes of data at a frequency of 156.25MHz, and outputs data at a frequency of 156.25MHz in a parallel pipeline operation mode, and performs data processing according to the position of the bitmap in the FAST protocol Therefore, it can avoid the huge delay caused by the serial processing method t...

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Abstract

The invention provides a 10-gigabit communication data parallel analysis method and a device based on the quick protocol. The huge delay of a serial processing mode to data delay can be avoided, hardware parallel acceleration is achieved, a client can obtain first-hand information of an exchange in a quicker mode, market opportunities are preempted, and profits are created for the client. A hardware parallel processing system is built by using an FPGA processing chip. The method comprises the following steps: (1) starting; (2) data receiving: 16 bytes of data are received at the frequency of 156.25 M Hz; (3) parallel data decoding is carried out, and output is carried out at the frequency of 156.25 M Hz in a parallel line production mode; (4) carrying out data distribution according to the position of the bitmap in the quick protocol; and (5) ending.

Description

technical field [0001] The invention relates to the technical field of 10 Gigabit Ethernet communication data processing, in particular to a parallel analysis method of 10 Gigabit communication data based on FAST protocol, and a parallel analysis device of 10 Gigabit communication data based on FAST protocol. Background technique [0002] In financial markets, the earlier an order arrives at an exchange, the more likely it is to be traded successfully. In this context, high-frequency trading has become more and more popular. Therefore, in the electronic financial data transmission path, the delay factor is very important. FAST (Financial Information Exchange Adapted fpr Streaming) financial protocol is one of the important technical backgrounds of high-frequency trading. It can compress financial data and reduce the bandwidth and time required for data transmission. [0003] In high frequency trading systems, time is money. The exchange must deliver market information to ...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L29/08
CPCH04L69/22H04L69/26H04L67/568
Inventor 郭高攀
Owner EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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