Test vector generation method and device and storage medium

A test vector and test pin technology, which is used in instruments, computing, electrical and digital data processing, etc., can solve the problems of reducing the detection efficiency, too many test vectors for test chips, etc., so as to improve the detection efficiency, reduce the number of production, and shorten the detection effect of time

Pending Publication Date: 2022-04-26
无锡玖熠半导体科技有限公司
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AI Technical Summary

Problems solved by technology

[0004] The application provides a test vector generation method, device and storage medium, which solves the problem that the existing test chip has too many test vectors and reduces the detection efficiency

Method used

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  • Test vector generation method and device and storage medium
  • Test vector generation method and device and storage medium
  • Test vector generation method and device and storage medium

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Embodiment Construction

[0022] In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0023] The "plurality" mentioned herein means two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and / or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently. The character " / " generally indicates that the contextual objects are an "or" relationship.

[0024] Design for Test (DFT, Design for Test) is a design technique in the field of integrated circuits, which implants some special structures into the circuit during the design stage, so that the circuit test can be performed after the design is completed. The scan chain technology in the testability design can check whether the internal s...

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PUM

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Abstract

The invention discloses a test vector generation method and device and a storage medium, and relates to the field of chips.The method comprises the steps that a test netlist of a test chip is obtained, and the test netlist comprises test nodes and corresponding test pins of all logic circuits in a scan chain of the test chip; determining a target test type of the test chip and a signal value of a test pin according to the test netlist, wherein the signal value is used for performing fault detection on a test node of the test chip; and performing logic simulation based on the test pins and the test values, generating test vectors of the test pins according to simulation output values, and merging the test nodes with the same test vectors to obtain a merged target test vector. The test vectors of the test nodes are generated in a mode of calibrating the test nodes in the test netlist, compared with a mode of detecting the test chip according to the number of test pins, redundancy elimination of the test vectors can be achieved, the number of times of detection can be reduced, and the test efficiency of chip detection can be improved.

Description

technical field [0001] The embodiments of the application relate to the field of chips, and in particular to a test vector generation method, device and storage medium of the present invention. Background technique [0002] The test vector is an excitation signal used to test the internal scan chain of the chip. In the chip design stage, in order to ensure the functional test of the chip, some logic circuits with special structure will be implanted inside the chip, so that the circuit test can be carried out after the design is completed. For example, scan chain (Scan Chain), etc., engineers can judge the performance and failure of the chip according to the test vector input and output results through the test machine, and prevent the damaged chip from flowing into the next stage and causing greater losses. [0003] In related technologies, in order to achieve effective test coverage, test quantities are usually generated according to the number of input pins of a test chip...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3308G06F30/323G06F30/333
CPCG06F30/3308G06F30/323G06F30/333
Inventor 钱静洁
Owner 无锡玖熠半导体科技有限公司
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