Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for decoding data received from a data source using hardware configuration data received from the same data source

A hardware configuration and data technology, applied in data recording, electrical digital data processing, time or data compression/expansion, etc., can solve the problems of not providing real-time decoding performance, power consumption, and expensive digital signal processors.

Inactive Publication Date: 2004-12-01
INTERDIGITAL VC HLDG INC
View PDF2 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, recently proposed video coding schemes have shown that current general-purpose architectures and digital signal processors (DSPs) do not provide the performance required for real-time decoding, especially when high-definition video is considered
Additionally, current general-purpose architectures and digital signal processors (DSPs) are expensive and power-hungry

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for decoding data received from a data source using hardware configuration data received from the same data source

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] Reconfigurable architectures allow the implementation of arbitrary logic functions, covering a wide range of cost, complexity, and performance. Therefore, the present invention is based on the idea that these reconfigurable architectures can provide the decoders required by recent or future multimedia decoding schemes at a reasonable cost level cheaper than a high-performance general-purpose processor or a high-performance DSP. processing power. A reconfigurable architecture for multimedia decoding will include a programmable HW, but may also include dedicated HW and SW programmable units such as a Reduced Instruction Set Computer (RISC) or other processors such as array processors, etc. Therefore, implementing a multimedia decoder on a reconfigurable architecture may require two data streams: the configuration data stream for the reconfigurable HW; and the SW program. However, it is also possible to reduce to just the HW configuration flow or just the SW procedure. F...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Today the storage of audiovisual (AV) data on storage media employs standardized coding schemes, e.g. MPEG-2. End user devices for AV presentation, like disc players, contain dedicated decoders implemented in hardware, which are able to decode data streams complying with the respective standard. The efficiency of this decoding methodology relies on the standardization of appropriate coding schemes. Proprietary coding schemes may be more efficient by being adapted to the content, or may be used for content protection or optional features. Using reconfigurable decoder hardware, storing the configuration data for the actual decoder on the same storage medium as the AV data, and downloading the data to configure the player can be used to implement proprietary coding schemes. Such schemes require appropriate player hardware, suitable to execute a downloaded decoder under real-time conditions, and a standardized format to store the decoder configuration data.

Description

technical field [0001] The present invention relates to a method for decoding data read from a data source, such as a storage medium, using reconfigurable hardware. Background technique [0002] A hardware architecture dedicated to a particular user may be implemented as a reconfigurable device, or as a non-reconfigurable device, such as an Application Specific Integrated Circuit (ASIC) or the like. A reconfigurable device is generally defined as a device whose computing architecture is defined after production, and can often be redefined. Examples include: Field Programmable Gate Arrays (FPGAs), which provide complete flexibility in terms of hardware (HW). However, a variety of reconfigurable architectures have been developed or are being developed that differ from typical FPGAs but satisfy common definitions. Although not as efficient as ASICs, reconfigurable architectures allow arbitrary logic functions to be implemented. [0003] In addition, general-purpose hardware ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/10G06F21/60G06F21/62G11B20/00G11B20/10
CPCG11B20/10527G11B20/10G11B20/00007
Inventor 延斯·维滕堡海因策-维尔纳·克森赫伯特·许策
Owner INTERDIGITAL VC HLDG INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products