Programmable frequency divider with symmetrical output

A frequency divider and frequency division value technology, which is applied in the direction of instruments, power oscillators, static memory, etc., to achieve the effect of less power and less physical area

Inactive Publication Date: 2005-11-30
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The extra circuitry limits the performance of the divider slightly due to the added load, but ensures that the transitions go through all unique states

Method used

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  • Programmable frequency divider with symmetrical output
  • Programmable frequency divider with symmetrical output
  • Programmable frequency divider with symmetrical output

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Embodiment Construction

[0048] (programmable divider)

[0049] The block diagram of FIG. 7 shows an asymmetric LFSR-based frequency divider circuit 107 cascaded in series with a symmetrical divide-by-two circuit 108 . Although the range of division values ​​is doubled in this implementation compared to the single LFSR divider 104 shown in FIG. 5, the resolution is halved. Additionally, the ability to perform frequency division with odd frequency division values, ie, 3, 5, 7, etc., is sacrificed. The final divider state transition table 110 for the cascaded asymmetric and symmetric dividers is shown in FIG. 10 . Therefore, it is desirable to provide a frequency division circuit capable of performing frequency division at high frequency division values ​​without losing odd frequency division values ​​in the process.

[0050] FIG. 11 shows a block diagram of a programmable high-speed frequency divider circuit 111 capable of recovering odd division values ​​of LFSR-based frequency dividers in accordanc...

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Abstract

A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Description

technical field [0001] The present invention relates to the field of integrated circuit frequency dividers, and in particular to the implementation of symmetrical and fully programmable frequency dividers using high speed linear feedback shift registers (LFSR). Background technique [0002] In its most basic implementation, a frequency divider circuit will accept an input signal with a given frequency and provide an output signal with a lower frequency. The relationship between the output and input signal frequencies is in the form of a programmable ratio, ie the frequency of the output signal will be the frequency of the input signal divided by a factor N. This factor, known as the "divider value" of the divider circuit, is programmable through the input 'control' signal to the divider. These control signals are digital in nature and can take on the value '1' or '0', and the number of control signals will determine the number of 'division modes' of the frequency divider, t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/64G11C19/00H03B19/00
CPCG11C19/00
Inventor 约翰·S.·奥斯汀马修·T.·索贝尔
Owner GLOBALFOUNDRIES INC
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