Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same

a technology of semiconductor devices and capacitance, applied in semiconductor devices, diodes, electrical apparatus, etc., can solve problems such as series resistance increase, and achieve the effect of suppressing short channel effect and preventing electrical characteristic from being deteriorated

Inactive Publication Date: 2006-11-30
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor device with an insulated gate type transistor and an insulated gate type capacitance that have separate electrical characteristics without deteriorating each other. This is achieved by selectively forming a gate insulating film and a gate electrode on a semiconductor substrate, with the insulated gate type transistor having pocket regions to suppress a short channel effect and the insulated gate type capacitance having no region of a reverse conductivity type to that of the extraction electrode regions in a vicinal region to prevent deterioration of its electrical characteristics. Additionally, the impurity concentration in the surface of the body region for a capacitance is different from that in the surface of the body region for a transistor to enhance design flexibility."

Problems solved by technology

Therefore, there has been a problem in that a series resistance is increased.

Method used

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  • Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
  • Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same
  • Semiconductor device including insulated gate type transistor and insulated gate type capacitance, and method of manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0062]FIG. 1 is a sectional view showing a structure of a semiconductor device having a MOS transistor and a variable capacitance according to a first embodiment of the present invention.

[0063] As shown in FIG. 1, an NMOS transistor Q1, a PMOS transistor Q2, an N-type variable capacitance C1 and a P-type variable capacitance C2 are formed in an NMOS formation region A1, a PMOS formation region A2, an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4, respectively. Each of the formation regions Al to A4 is isolated by an isolating film (not shown) or the like. Moreover, well regions 11, 21, 31 and 41 to be body regions are formed in the formation regions A1, A2, A3 and A4, respectively.

[0064] In the NMOS formation region A1, a gate oxide film 12 is selectively formed on a surface of the P well region 11 and an N+-type gate electrode 13 is formed on the gate oxide film 12. N+ source-drain regions 14 and 14 are formed to interpose a...

second embodiment

[0095]FIG. 8 is a sectional view showing a structure of a semiconductor device having a MOS transistor and a variable capacitance according to a second embodiment of the present invention.

[0096] As shown in FIG. 8, a buried oxide film 4 is formed on a support substrate 3, and an SOI layer 5 formed on the buried oxide film 4 is isolated into an NMOS formation region A1, a PMOS formation region A2, an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 through an isolating film (not shown) or the like.

[0097] An NMOS transistor Q1, a PMOS transistor Q2, an N-type variable capacitance C1 and a P-type variable capacitance C2 which have the same structures as those of the first embodiment are formed in the NMOS formation region A1, the PMOS formation region A2, the N-type variable capacitance formation region A3 and the P-type variable capacitance formation region A4, respectively.

[0098] In the semiconductor device according to the seco...

third embodiment

[0102]FIG. 11 is a sectional view showing a structure of a semiconductor device having a MOS transistor and a variable capacitance according to a third embodiment of the present invention.

[0103] As shown in FIG. 1, variable capacitances C3 and C4 of an inversion type are provided in place of the variable capacitances C1 and C2 of an accumulation type. More specifically, the structure according to the third embodiment is different from the structure according to the first embodiment shown in FIG. 1 in that a P well region 30 is provided in place of the N well region 31 and an N well region 40 is provided in place of the P well region 41.

[0104] More specifically, the N-type (N+ gate / P− body / N+S / D type) variable capacitance C3 and the P-type (P+ gate / N− body / P+S / D type) variable capacitance C4 have structures equivalent to the structures of the NMOS transistor and the PMOS transistor, and are different from the NMOS transistor Q1 and the PMOS transistor Q2 in that pocket regions corr...

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Abstract

A semiconductor device includes a semiconductor substrate, an insulated gate type transistor formed in the semiconductor substrate, and an insulated gate type capacitor formed in the semiconductor substrate. The insulated gate type transistor includes a gate insulating film of the transistor selectively formed on the semiconductor substrate, a gate electrode of the transistor formed on the gate insulating film of the transistor, and source-drain regions formed to interpose a body region of the transistor provided under the gate electrode of the transistor in a surface of the semiconductor substrate. The insulated gate type capacitor includes a gate insulating film of the capacitor selectively formed on the semiconductor substrate, a gate electrode of the capacitor formed on the gate insulating film of the capacitor, and extraction electrode regions formed to interpose a body region of the capacitor provided under the gate electrode of the capacitor in the surface of the semiconductor substrate. The extraction electrode regions have a common potential. The insulated gate type transistor has pocket regions of the transistor of a reverse conductivity type to that of the source-drain regions formed from the source-drain regions to a part of the body region of the transistor, the insulated gate type capacitor has no region of a reverse conductivity type to that of the extraction electrode regions in a vicinal region of the extraction electrode regions in the body region side of the capacitor, and the body region of the capacitor and the extraction electrode regions are formed to have different conductivity types from each other.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of U.S. patent application Ser. No. 10 / 200,523, filed Jul. 23, 2002, and claims priority to Japanese Patent Application No. 2001-254516, filed Aug. 24, 2001. The contents of U.S. patent application Ser. No. 10 / 200,523 are incorporated herein by reference in their entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device having an insulated gate type transistor and an insulated gate type capacitance and a method of manufacturing the semiconductor device. [0004] 2. Description of the Background Art [0005] In a transistor having a gate length of a subquarter micron or less, a pocket injecting process for forming pocket regions is executed in order to suppress a short channel effect. The pocket injection is also referred to as NUDC (Non Uniformly Doped Channel). [0006]FIG. 36 is a sectional view showing the pocket injecting process. A...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/76H01L29/78H01L21/265H01L21/74H01L21/8234H01L21/8238H01L27/06H01L27/08H01L27/092H01L29/94H10B12/00
CPCH01L21/26586H01L21/74H01L21/84H01L27/0629H01L27/0808H01L29/94H01L27/1203H01L29/1083H01L29/6659H01L29/7833H01L27/0811H01L29/78
InventorMAEDA, SHIGENOBUTAKASHINO, HIROYUKIOKA, TOSHIHIDE
OwnerRENESAS TECH CORP