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ESD protection circuit

a protection circuit and electrostatic discharge technology, applied in the direction of overvoltage protection resistors, varistors, emergency protection arrangement details, etc., can solve the problems of damage to the internal circuit, increased esd exposure of advanced ic devices,

Active Publication Date: 2015-03-03
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

An electrostatic discharge (ESD) event is an important reliability issue for integrated circuits (ICs).
However, the advanced IC devices also become more susceptible to ESD damage.
ESD phenomenon occurs when excess charges are transmitted from the I / O pin to the integrated circuit too quickly, which damages the internal circuit.

Method used

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Embodiment Construction

[0018]The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0019]FIG. 1 shows an electrostatic discharge (ESD) protection circuit 100 according to an embodiment of the invention. The ESD protection circuit 100 is implemented in an integrated circuit (IC), wherein the ESD protection circuit 100 can provide ESD protection for an input / output (I / O) pad 20 of the IC. The ESD protection circuit 100 comprises an impedance device 110 and the clamp units 120, 130 and 140. In the IC, the ESD protection circuit 100 is coupled to a power pad 10 and a ground pad 30 via a power line L1 and a ground line L2, respectively. A power voltage VDD is applied to the power pad 10 and the ground pad 30 is grounded when the IC is operated in a normal...

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PUM

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Abstract

An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 557,553, filed on Nov. 9, 2011, and U.S. Provisional Application No. 61 / 595,956, filed on Feb. 7, 2012, the entireties of which are incorporated by reference herein.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit with high power supply rejection ratio (PSRR).[0004]2. Description of the Related Art[0005]An electrostatic discharge (ESD) event is an important reliability issue for integrated circuits (ICs). To meet component-level ESD reliability, on-chip ESD protection circuits are implemented in the input / output (I / O) cells and power / ground cells of complementary metal-oxide semiconductor (CMOS) ICs.[0006]With the continued miniaturization of IC devices, the current trend in the sub-micron CMOS technology is to produce inte...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01C7/12H02H1/00H02H1/04H02H3/22H02H9/06H02H3/20H02H9/04
CPCH02H3/20H02H9/046
Inventor HUANG, BO-SHIHCHEN, TSUNG-MINGCHUNG, YUAN-HUNG
Owner MEDIATEK INC