Method for forming doped areas under transistor spacers

a technology of transistor spacers and doped areas, which is applied in the direction of transistors, electrical devices, semiconductor devices, etc., can solve the problem of requiring a significant thermal budg

Active Publication Date: 2016-06-28
COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enables the formation of doped areas under the spacers in contact with the channel zone without overlapping, reduces the number of photolithography steps, and allows for the application of strain close to the channel, improving transistor performance.

Problems solved by technology

This thermal annealing step poses a problem to the extent that it requires a significant thermal budget.
Implant doping further causes a problem when the semi-conductor layer to be doped is based on a material that is different from that of the semi-conductor areas formed by epitaxy on either side of the gate.
There is then the problem of finding a new method, for forming a transistor with better performances and, improved as regards the aforementioned disadvantages.

Method used

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  • Method for forming doped areas under transistor spacers
  • Method for forming doped areas under transistor spacers
  • Method for forming doped areas under transistor spacers

Examples

Experimental program
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Embodiment Construction

[0051]An example method according to an embodiment of the invention, for fabricating a microelectronic transistor(s) device, will now be described in connection with FIG. 2A-2F.

[0052]The starting material for this method can be a semi-conductor on insulator type substrate, SOI (SOI for >) type for example, which comprises a semi-conductor support layer (not represented) on and in contact with an insulating layer (not represented) which can be silicon oxide based and arranged on and in contact with the support layer. The substrate further comprises a thin semi-conductor layer 103 situated on and in contact with said insulating layer.

[0053]This thin semi-conductor layer 103 can, for example, have a thickness of less than 20 nm and that may, for example, be approximately 12 nm.

[0054]Deposition steps of a dielectric gate layer 107 and of one or several layers 108, 109 of gate material(s), and then etching of these layers are then carried out in order to form a transistor gate 110 (FIG. ...

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Abstract

Method for fabricating a transistor comprising the steps consisting of:forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone,forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor,removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers,forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.

Description

TECHNICAL FIELD AND STATE OF PRIOR ART[0001]The MOS field effect transistor is based on charges concentration modulation in a channel zone by means of a gate electrode situated above the channel and insulated from all other regions of the device by a dielectric gate. Such a transistor moreover comprises source and drain regions arranged on each side of the channel zone and which can be formed in the same semi-conductor layer as that in which the channel is located.[0002]In order to improve the transistor performances, a solution consists of implementing raised source and drain regions 11, 12, that is to say which are at least partially formed in semi-conductor regions extending either side of a gate 10, above a semi-conductor layer 7 in which a channel 8 is formed (FIG. 1A).[0003]The raised source 11 and drain 12 regions are generally formed by epitaxial growth during which they may be doped.[0004]Insulating spacers 13a and 13b arranged against the lateral sides of the gate are prov...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): H01L21/336H01L29/417H01L29/786H01L29/78H01L21/02H01L29/66H01L29/16H01L21/28H01L21/265H01L29/161
CPCH01L29/66568H01L21/02532H01L21/02592H01L21/02667H01L29/16H01L29/41766H01L29/66628H01L29/66636H01L29/66772H01L29/78654H01L21/26506H01L21/26586H01L21/2807H01L21/28088H01L29/161H01L29/6653H01L29/6656H01L29/7848
InventorBATUDE, PERRINEHARTMANN, JEAN-MICHELSKLENARD, BENOITVINET, MAUD
OwnerCOMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES