Projecting circuits from electrostatic dischange

Abstract

A circuit and method for protecting a circuit from electrostatic discharge damage. Wherein the method includes detecting whether a power supply of a protected circuit is activated and disabling an output driver of the circuit when the circuit power is activated. The ESD protection circuit includes an ESD sensing circuit and a disabling circuit. The ESD sensing circuit includes an RC circuit connected between VDD and VSS and a first inverter connected between a second inverter and a node connected to a resistor and a capacitor in the RC circuit. The disabling circuit includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor receives an EN signal from the second inverter, and the first NMOS transistor receives an EN signal from the first inverter. The first PMOS transistor is connected to a second PMOS transistor to VDD when EN is low, and the first NMOS transistor is connected to a second NMOS transistor to VSS when EN is high.

Description

technical field [0001] The present invention relates to a semiconductor chip and its built-in protection circuit, in particular to a protection circuit and a method for protecting the semiconductor chip from electrostatic discharge (EletroStatic Discharge; hereinafter referred to as ESD). Background technique [0002] We all know that many situations in daily life can cause static electricity. Static electricity is generated when electrons are transferred from one object to another, giving one object a negative charge and another object a positive charge. For example, a person's skin surface has an electrostatic potential, whether positive or negative, that can be released to an object with a different electrostatic potential. Electrostatic discharge or "shock" occurs when the electric field between charged objects of opposite potentials collapses. An ESD event is characterized by its high voltage, while the current or charge involved is quite small. [0003] For example,...

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Problems solved by technology

[0010] However, even though known ESD protection circuits pass the above tests and still function normally in most cases, these ESD protection circuits may still fail in some difficult-to-reproduce situations

The cause of the failure is thought to be that the chip was activated due to the discharge of the ESD event

For example, when an ESD pulse is applied from the bonding pad 14 to VSS, it may cause a current to flow from the PMOS parasitic diode 30 to VDD to start the chip

If the gate of the NMOS transistor 24 in the output driver 18 is at a high potential at this time, the transistor 24 will be driven into a conduction state when the chip is started, and a large amount of current will flow into a small area of ​​the transistor 24 and damage the entire output driver 18.

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