Bolt lock device having sensing amplifier

Abstract

The present invention relates to a crosspiece lock with a sensing amplifier, the crosspiece includes an input circuit, a sensing amplifier, a crosspiece locking circuit and an output circuit; wherein, the crosspiece locking circuit adopted by the present invention reduces the frequency variation of an output signal and a complementary output signal, thereby saving a lot of power. The present invention does not produce surge waves and error actions; and is more suitably applied to a high-speed circuit.

Description

technical field [0001] The present invention relates to a latch, in particular to a sense amplifier-based latch with a sense amplifier, which is applied to a DRAM circuit. Background technique [0002] FIG. 1 is a schematic diagram of a simplified data path from a memory cell 110 to a data line sense amplifier according to a conventional dynamic random access memory (DRAM) circuit architecture. Referring to FIG. 1, after the transistor 112 is turned on (turnon) through the word line WL, the bit data placed in the capacitor C passes through the long bit line from the memory cell (memory cell) 110. BL, bit switch (bit switch) 122 controlled by control signal BSEN, local data line (local data line) LDQ, main data switch (main data switch) (or transmission gate) 124 controlled by control signal SWEN, main When the data line (master data line, MDQ) is finally passed to the I / O data bus, the signal is already very weak. Therefore, in the existing DRAM architecture, there are two...

AI Technical Summary

Problems solved by technology

Since the output signal DT / DTB is toggled repeatedly, more power is consumed, and glitches are more likely to occur, which in turn is more likely to cause malfunctions

On the other hand, because the cycle of the period data_window is too short, the complexity of the control circuit that can correctly capture the data in the output signal DT / DTB will be relatively high

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