Process for producing semiconductor device
一种制造方法、半导体的技术,应用在半导体/固态器件制造、半导体器件、运输和包装等方向,能够解决不能引线接合、减低、半导体装置生产率低等问题,达到抑制成本提高的效果
Inactive Publication Date: 2010-12-01
NITTO DENKO CORP
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- Abstract
- Description
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Problems solved by technology
With regard to the manufacturing method of the conventional semiconductor device, the following problems are pointed out: when bonding the semiconductor element and the substrate, the lead frame, or the semiconductor element (hereinafter referred to as the substrate, etc.), if the paste resin is used, After connecting the semiconductor element and the substrate (die attach), the paste resin overflows and contaminates the connection base part of the substrate, so that wire bonding cannot be performed
However, when using this process to produce laminated semiconductor devices, the semiconductor chip used is easily broken, which reduces the yield
As a result, there are problems of low productivity and high cost of semiconductor devices
Method used
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Embodiment 1
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Abstract
A process for semiconductor device production in which three-dimensional mounting through a spacer is conducted without necessitating a novel device for fixing the spacer to an adherend and by which semiconductor devices can be produced in high yield and at low cost. The invention relates to the process for semiconductor device production employing an adhesive sheet serving as a spacer. It is characterized in that the adhesive sheet serves as a spacer comprising a spacer layer having an adhesive layer on at least one side thereof, the spacer is subjected to dicing to form a chip-form spacer having an adhesive layer and a step in which the spacer is fixed to an adherend through the adhesive layer.
Description
Manufacturing method of semiconductor device technical field The present invention relates to a method of manufacturing a semiconductor device using an adhesive sheet for a gasket, an adhesive sheet for a gasket used in the method, and a semiconductor device obtained by the method. Background technique In response to demands for miniaturization and higher functionality of semiconductor devices, the wiring width of power supply lines and the spacing between signal lines arranged over the entire main surface of a semiconductor chip (semiconductor element) are becoming smaller. Therefore, an increase in impedance and signal interference between signal lines of different nodes become the main factors that hinder the sufficient performance of the semiconductor chip in terms of operating speed, operating voltage margin, and electrostatic breakdown resistance. In order to solve these problems, an interposer structure in which semiconductor elements are laminated has been proposed...
Claims
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Patent Timeline

Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/52C09J7/02C09J7/28
CPCH01L2224/85205C09J7/0292H01L2924/01047H01L25/0657H01L2224/48227H01L2924/20104H01L2924/01029H01L2924/20105H01L2924/01051H01L2924/01016H01L2224/45147H01L2924/0132H01L2924/01056H01L2924/01079H01L2924/01004H01L2224/48091H01L2224/73265H01L2924/01006H01L2224/32145H01L2924/20106H01L2924/01019H01L2224/45124C09J2201/128H01L24/29H01L2924/01014H01L2924/01074H01L24/27H01L25/50H01L2924/0103H01L2225/0651H01L2924/20107H01L2924/0105H01L2924/20103H01L24/32H01L2224/32245H01L2924/0102H01L2225/06575C09J2203/326H01L2224/45144H01L2924/01013H01L2924/01005H01L2924/01028H01L2924/01033H01L2924/01082H01L2224/83191H01L2924/01046H01L2224/32225H01L24/45H01L2924/3011H01L2924/01015C09J7/0207H01L2224/92247C09J2201/36H01L2924/01024H01L2924/15747H01L2924/181H01L24/73C09J7/38C09J7/28Y10T428/28C09J2301/208C09J2301/124H01L2224/2612H01L2924/00014H01L2924/00012H01L2924/01026H01L2924/00H01L2924/3512H01L21/48
Inventor 三隅贞二松村健高本尚英三木翼
Owner NITTO DENKO CORP
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