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Method for forming micro-pattern of semiconductor device

A semiconductor and micro-patterning technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve problems such as no application of hole patterns

Inactive Publication Date: 2012-07-11
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current state of the art allows the self-aligned double patterning technique to be widely applied to line patterns, but generally not to hole patterns

Method used

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  • Method for forming micro-pattern of semiconductor device
  • Method for forming micro-pattern of semiconductor device
  • Method for forming micro-pattern of semiconductor device

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Embodiment Construction

[0016] Other objects and advantages of the present invention can be understood from the following description and become apparent with reference to the embodiments of the present invention.

[0017] Embodiments of the present invention relate to a method of forming a micro pattern in a semiconductor device, which can form a micro hole pattern having a pitch smaller than an allowable resolution using a self-aligned double patterning technique.

[0018] Additionally, the method includes performing a photolithographic technique once. Thus, an undesired critical dimension (CD) that often occurs due to exposure mask misalignment when using typical double patterning techniques can be reduced. Also, since the number of times the exposure process is performed is reduced, cost can be reduced.

[0019] Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. ...

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Abstract

A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openingsusing the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns.

Description

[0001] related application [0002] This application claims priority from Korean Patent Application No. 10-2008-0112676 filed on November 13, 2008, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to semiconductor technology, and more particularly, to a method of forming a micropattern in a semiconductor device, wherein the microhole pattern is formed at a size smaller than allowable resolution. Background technique [0004] The semiconductor industry is rapidly developing as semiconductor devices become highly integrated and efficient. Such rapid development, in turn, has increased the need for large-scale integration and efficiency of semiconductor devices. [0005] The manufacture of semiconductor devices includes repeated implementation of deposition process, ion implantation process, photo process, etching process and cleaning process to form desired circuit patterns on semiconductor substrates an...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/768
CPCH01L21/0338H01L21/0337H01L21/0334
Inventor 金原圭
Owner SK HYNIX INC