Method for manufacturing semiconductor device

Abstract

The invention relates to a method for manufacturing a semiconductor device having tensile stress as well as pressure stress. The method comprises the following steps: providing a semiconductor substrate with a NMOS (N-channel metal oxide semiconductor) transistor and a PMOS (P-channel metal oxide semiconductor) transistor; depositing a tensile stress layer on the semiconductor substrate; depositing a compound hard mask layer on the tensile stress layer; removing the compound hard mask layer and the tensile stress layer on the PMOS transistor; deposing the pressure stress layer; and removing the pressure stress layer and part of compound hard mask layer on the NMOS transistor, and making interconnected structure, wherein the compound hard mask layer is formed by combining at least two hardmask layers and the deposition rate of the hard mask layers is gradually increased on the surface of the semiconductor substrate. In the invention, when the compound hard mask layer is formed, the first hard mask layer can fully fill the slot between adjacent transistor grid electrodes, so as to avoid forming clearance and ensure the electric property of formed products. When the slot is filled, the hard mask layer is deposited at a high deposition rate so as to increase the production efficiency.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method including a semiconductor device with tensile stress and a semiconductor device with compressive stress on the same semiconductor substrate. Background technique [0002] As the semiconductor technology enters the sub-micron era, the issue of increasing the drive current of MOS devices has been paid more and more attention. The increase of the drive current will greatly improve the delay time (time delay) of components and increase the response rate of components. [0003] Controlling stress is an effective way to improve carrier mobility in MOS devices, especially field effect transistors, and to increase transconductance (or reduce series resistance) of MOS devices, thereby increasing drive current. [0004] When stress is applied to the channel of a semiconductor transistor, the mobility of the carriers changes from their original val...

AI Technical Summary

Problems solved by technology

This is because with the continuous development of semiconductor technology, the distance between the gates of two adjacent transistors is getting closer and closer, making the width of the trench formed between adjacent gates narrower and narrower. The formation of a hard mask layer at a high rate will not be able to fully fill the trenches between adjacent gates, resulting in gaps. When other structures are formed later, the gaps cannot be completely filled, and there will be defects on the final semiconductor product, which will affect Electrical performance of the device, such as short circuits between interconnect lines due to the presence of voids

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