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Formation method of double trench isolation structure

A double-trench isolation and trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc.

Active Publication Date: 2016-06-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since the etchant continues to etch the buried insulating layer 101 until the substrate silicon 100, the SOI device is etched through

Method used

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  • Formation method of double trench isolation structure
  • Formation method of double trench isolation structure
  • Formation method of double trench isolation structure

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Embodiment Construction

[0018] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0019] refer to Figure 6 , 6A, 6B, where, attached Figure 6 is a top view of the semiconductor structure, Figure 6A , 6B is a cross-sectional schematic view of the semiconductor structure in the direction of AA and BB respectively; first, a semiconductor substrate is provided, and the semiconductor substrate is silicon on insulator (Silicon On Insulator, SOI), including the substrate silicon 200, and the substrate is located in turn Buried insulating layer 201 on silicon 200 , top layer silicon 202 . The material of the buried insulating layer 201 is, for example, silicon oxide with a thickness of, for example, 1500 angstroms, and the thickness of the top silicon layer 202 is, for example, 1000 angstroms. Subsequently, a liner layer 203 and a hard mask layer 204 are sequentially formed on the top layer of silicon 202. The material of...

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PUM

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Abstract

A method for forming a double trench isolation structure includes: providing silicon-on-insulator comprising substrate silicon, a buried insulating layer and a top layer of silicon, and sequentially forming a liner layer, a hard mask layer and a second mask layer on the top layer of silicon; Using the patterned second mask layer as a mask, etching the hard mask layer to expose the liner layer to form a second opening; removing the second mask layer, forming a second opening on the hard mask layer and in the second opening Sacrificial layer; removing part of the sacrificial layer to expose the hard mask layer; forming a patterned first mask layer on the hard mask layer and the sacrificial layer, etching the hard mask layer, pad layer and part of the top layer of silicon Forming the first opening to a set depth, the second opening area partially overlaps the first opening area; removing the sacrificial layer and the first mask layer; etching the first opening to expose the buried insulating layer to form a first trench, and etching The second opening and part of the top silicon form a second trench. The method avoids the defect that the buried insulating layer in the overlapping region of the first trench and the second trench is etched through.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a double trench isolation structure. Background technique [0002] Integrated circuits based on silicon-on-insulator (Silicon On Insulator, SOI) have the characteristics of low voltage, low power consumption, high speed, and high integration, and are the mainstream process for the development of semiconductor technology to the nanoscale. A bipolar transistor is a very important device unit in an analog integrated circuit. A bipolar transistor based on a silicon-on-insulator process needs to use a dual-trench isolation (Dual-STI) structure, which requires a special manufacturing method. For existing methods of forming double trench isolation structures, refer to the appended figure 1 , 1A, 1B to attached Figure 5 , 5A, 5B. [0003] refer to figure 1 , 1A, 1B, where, attached figure 1 is a top view of the semiconductor structure, Fig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/308
Inventor 高超
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP