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Method for forming double-trench isolation structure

A technology of double trench isolation and hard mask layer, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc.

Active Publication Date: 2015-04-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since the etchant continues to etch the buried insulating layer 101 until the substrate silicon 100, the SOI device is etched through

Method used

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  • Method for forming double-trench isolation structure
  • Method for forming double-trench isolation structure
  • Method for forming double-trench isolation structure

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Embodiment Construction

[0024] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0025] refer to Image 6 , 6A, 6B, where, attached Image 6 is a top view of the semiconductor structure, Figure 6A , 6B is a cross-sectional schematic view of the semiconductor structure in the direction of AA and BB; first, a semiconductor substrate is provided, and the semiconductor substrate is silicon on insulator (Silicon On Insulator, SOI), including the substrate silicon 200, and sequentially located Buried insulating layer 201 on substrate silicon 200 , top layer silicon 202 . The material of the buried insulating layer 201 is, for example, silicon oxide with a thickness of, for example, 1500 angstroms, and the thickness of the top silicon layer 202 is, for example, 1000 angstroms. Subsequently, a liner layer 203 and a hard mask layer 204 are sequentially formed on the top layer of silicon 202. The material of the liner layer ...

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Abstract

The invention discloses a method for forming a double-trench isolation structure, which comprises the following steps of: providing a silicon-on-insulator (SOI) comprising substrate silicon, a buried insulating layer and top silicon, and forming a pad layer, a hard mask layer and a first mask layer on the top silicon; taking the patterned first mask layer as a mask, and etching the hard mask layer, the pad layer and the top silicon until the buried insulating layer is exposed so as to form a first opening; removing the first mask layer, and forming a sacrifice layer on the hard mask layer and in the first opening; removing partial sacrifice layer until the hard mask layer is exposed; forming a patterned second mask layer on the hard mask layer and the sacrifice layer, taking the patterned second mask layer as a mask, and etching the hard mask layer to expose the pad layer so as to form a second opening, wherein the area of the second opening is partially overlapped with the area of the first opening; etching the pad layer and partial top silicon to reach the set depth of a second trench; and removing the first mask layer, the hard mask layer and the sacrifice layer. The method overcomes the defect that the buried insulating layer in the overlapped area of the first trench and the second trench is etched.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a double trench isolation structure. Background technique [0002] Integrated circuits based on silicon on insulator (Silicon On Insulator, SOI) have the characteristics of low voltage, low power consumption, high speed, and high integration, and are the mainstream process for the development of semiconductor technology to the nanoscale. A bipolar transistor is a very important device unit in an analog integrated circuit. A bipolar transistor based on a silicon-on-insulator process needs to use a dual-trench isolation (Dual-STI) structure, which requires a special manufacturing method. For existing methods of forming double trench isolation structures, refer to the appended figure 1 , 1A, 1B to attached Figure 5 , 5A, 5B. [0003] refer to figure 1 , 1A, 1B, where, attached figure 1 is a top view of the semiconductor structure, Fig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76H01L21/762
Inventor 高超
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP