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Field effect transistor having nanostructure channel

A technology of field-effect transistors and nanostructures, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., can solve problems such as difficulty in placing tiny structures

Inactive Publication Date: 2015-05-20
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It will be appreciated that the placement of these tiny structures is difficult at the scale of current CMOS technology

Method used

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  • Field effect transistor having nanostructure channel
  • Field effect transistor having nanostructure channel
  • Field effect transistor having nanostructure channel

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Embodiment Construction

[0021] The structures disclosed herein (and methods of forming such structures) employ pre-patterned embedded catalyst lines and a replacement gate process to provide photolithographically defined catalyst particle source / drain junctions that are self-aligned to the gate. By growing nanostructures precisely at desired locations using precisely positioned catalyst particles, the need to grow, obtain, and subsequently place nanostructures can be eliminated. Accordingly, field effect transistors (FETs) having nanostructured channels can be formed.

[0022] Now refer to figure 1 , which shows an example of the structure in the FET production process according to a preferred embodiment of the present invention, wherein it should be combined with Figure 2-Figure 10 right figure 1 to understand. The wafer includes a substrate 102 . Substrate 102 may be formed of any material, but in one embodiment is made of insulating silicon dioxide (SiO2) on top. 2 ) of silicon formation.

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Abstract

A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.

Description

technical field [0001] The present invention relates to transistors, and more particularly to field effect transistors. Background technique [0002] Due to the high carrier mobility and small size that nanostructures such as carbon nanotubes or semiconductor nanowires can offer, switching devices based on such nanostructures have great potential. However, one of the many challenges that nanostructure-based technologies must overcome is compatibility with the high layout densities currently supported by conventional silicon complementary metal-oxide-semiconductor (CMOS) technology. To achieve high layout density, the nanostructures and the source / drain and gate contacts to the switching devices established around each nanostructure should be precisely positioned. In silicon CMOS, this precise positioning is achieved by the source / drain junction self-aligning with the gate and the photolithographic resolution of the active region. [0003] Currently, there are several diffe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L51/00H01L51/05
CPCB82Y10/00H10K71/164H10K85/221H10K10/464H10K10/484H01L29/0673H01L29/775H01L29/78H10K71/10
Inventor J·常M·奎洛恩E·A·约瑟夫
Owner GLOBALFOUNDRIES INC