Power-on-reset circuit with low power consumption

Abstract

Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit (100) includes a detector (104) that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator (106) generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor (108) detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.

Description

technical field

[0001] Aspects of the invention relate to power-on reset circuits. In some embodiments of the present invention, the power-on reset circuit has low or no static power consumption. Background technique

[0002] Logic circuits, such as the synchronous logic of a microcontroller, usually, but not always, need to be initialized to be in a known state when powered up and / or powered down. To provide this initialization, a power-on-reset (POR) device may be used in a circuit, such as a microcontroller with associated logic. The circuitry of the POR device generates a reset pulse that initializes the logic points after the logic circuit's power supply ramps up. This reset pulse ensures that the logic starts in a known state, making the start-up of circuit behavior predictable.

[0003] A power-on-reset circuit can function by monitoring the supply voltage and generating a pulse if the supply voltage transitions from a low state to a high state. This pulse can be ...

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