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Hybrid address mapping method for multi-core multi-threading processor
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A multi-threaded processor, address mapping technology, applied in the direction of memory address/allocation/relocation, etc., can solve the problem of high probability of the same row, and achieve the effect of wide application range and low probability of body conflict
Active Publication Date: 2015-01-14
NAT UNIV OF DEFENSE TECH
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If XOR-based page cross-mapping is used, although the XOR operation (⊕) can be used to discrete, but because the bank address is fixed at the highest bit, the same as the page cross-mapping method, the addresses of all base address streams in this mapping method There is a high probability that the ranks of
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Embodiment 1
[0042] The implementation steps of the hybrid address mapping method for multi-core multi-thread processors in this embodiment are as follows:
[0043] 1) Map the access address from high bit to low bit as follows figure 1 shown
[0044] high ,bank,rank,channel,col low ,byte>
[0045] Among them, row represents the row address, col high Represents the high bit of the column address, bank represents the body address, rank represents the row address, channel represents the channel address, col low Represents the low bit of the column address, byte represents the byte index address, and the low bit of the column address is used to store the Cache line burst access address (Cacheline burst address) and burst access internal word address (burst internal word address);
[0046] 2) Perform a bit operation to obtain a new memory access address according to the row address in the memory access address obtained through mapping, and perform access to the SDRAM according to the new me...
Embodiment 2
[0054] The implementation steps of the hybrid address mapping method for multi-core multi-thread processors in this embodiment are basically the same as in Embodiment 1, the main difference being step 2), and the detailed steps of step 2) include:
[0055] B1) Partial addresses are respectively intercepted from the row address as the first part of the row address and the second part of the row address;
[0056] B2) performing XOR operation on the first part of row address and body address to obtain a new body address, and performing XOR operation on the second part of row address and row address to obtain a new row address;
[0057] B3) Replace the bank address in the originally mapped memory access address with the new bank address and the new bank address, and access the SDRAM according to the replaced memory access address.
[0058] In this embodiment, the first part of the row address is located at the high side of the row address; the second part of the row address is loc...
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Abstract
The invention discloses a hybrid address mapping method for a multi-core multi-threading processor, which is as follows: 1) sequentially mapping fetching addresses into row, colhigh, bank, rank, channel, collow and byte from high order to low order with the low order of a column address used for storing a Cache row burst access address and a burst access inside word address; and 2) carrying out bit operation to obtain a new fetching address according to the row address mapped in the fetching address and accessing SDRAM according to the new fetching address. The hybrid address mapping method can discrete the row arrangement in the fetching, simultaneously map the neighboring logical pages in the address space to multiple entities, so as to access different row and entity physical pages in a streamlined way; and the hybrid address mapping method has the advantages of low collision probability and wide application range.
Description
technical field [0001] The invention relates to an address mapping method for a multi-core microprocessor storage system, in particular to an address mapping method for a storage system with a large number of threads and concurrent access by multiple base address streams in a multi-core processor. Background technique [0002] At present, the mainstream off-chip memory uses DDR2 and DDR3 memory (hereafter collectively referred to as DDR), which are all based on SDRAM (Synchronous Dynamic Random Access Memory). DDR external memory is composed of DDR SDRAM of Dual In-line Memory Module (DIMM for short). Each DDR memory stick DDR SDRAM is a row (rank), body (bank), row (row) and column (column, referred to as col) index four-dimensional storage structure. The storage controller generally transmits memory access instructions to SDRAM in the order of first-in-first-out. This method of scheduling according to program order is simple to implement, but due to memory bank competitio...
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