Memory body and manufacturing method thereof

Abstract

The invention provides a memory body and a manufacturing method thereof. The manufacturing method comprises the following steps of forming multiple stacked structures on a substrate extending in a first direction, wherein each stacked structure comprises a plurality of first insulation layers and a plurality of second insulation layers, the first insulation layers are stacked on the substrate and the second insulation layers are respectively arranged between the adjacent first insulation layers; forming a plurality of troughs extending in the first direction in each stacked structure, wherein the troughs are located at two opposite sides of the each second insulation layer; filling a first conductor layer in each trough, and forming a plurality of charge storage structures extending in a second direction on the stacked structures, and forming a second conductor layer on each charge storage structure. According to the memory body and the manufacturing method thereof provided by the invention, as the insulation layers with different etching velocities are stacked on the substrate alternatively, and as the insulation layers of the etched part are adopted to form an area to fill in a bit element line, the limit of the existing lithography can be broken through to form the bit element line with a smaller size, thereby improving the memory density of the memory body.

Description

technical field [0001] The invention relates to a memory and a manufacturing method thereof, in particular to a memory with relatively high memory density and a manufacturing method thereof. Background technique [0002] Since non-volatile memory has the advantage that the stored data will not disappear after the power is turned off, many electrical products must have this kind of memory to maintain the normal operation of the electrical product when it is turned on. [0003] As the size of electronic components shrinks, so does the size of memories made up of arrays of memory cells. However, limited by the current lithography technology, the general two-dimensional memory cell array is also limited in size reduction (for example, reducing the distance between adjacent memory cells). In addition, due to the reduction in the size of the memory cells, the memory density is also reduced. [0004] In order to increase the data storage capacity of the memory, the three-dimensio...

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Problems solved by technology

However, for the current three-dimensional memory cell array process, it has high complexity, and the size reduction is still limited by the existing lithography technology

[0005] It can be seen that the above-mentioned existing memory and its manufacturing method obviously still have inconvenience and defects in product structure, manufacturing method and use, and need to be further improved urgently.

In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve

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