Interconnection structure and manufacturing method of the same

Abstract

The invention provides an interconnection structure and a manufacturing method of the interconnection structure. At first, a through hole is etched in an inter-lamination dielectric layer; and afterwards, after electro-coppering is finished in the through hole, the inter-lamination dielectric layer is removed and a second low k dielectric layer is deposited to prevent the conditions that low k media on two sides are damaged in the process of etching the through hole, and that low k media on the side of metal wiring below the through hole are damaged by stacking deviations on the etching condition. A metal blocking layer plays a role in an electrode when copper is electroplated to ensure that the copper vertically and upwards grows along the bottom of the through hole. The metal blocking layer can prevent the copper from filling gaps, and therefore good copper filling performance is obtained, and reliability and performance of a device are improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an interconnection structure and a manufacturing method thereof. Background technique [0002] The backend of the line (BEOL) process refers to the chip manufacturing stage when active devices (such as transistors) are interconnected with metal wiring. "Cu+dual damascenes process (DD, dualdamascenes process)+low k" is a multi-layer interconnection technology used in the semiconductor process of 90nm and below nodes. This technology uses Cu instead of traditional Al, which can greatly reduce Wiring resistance; use low-k dielectric (referring to lower dielectric constant <3.2) materials to replace traditional SiO 2 As an interlayer insulation, it can effectively reduce the interconnect capacitance and RC delay without reducing the wiring density, so that the chip works faster and reduces power consumption. [0003] A multilayer interconnection technology generally pr...

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