Wafer-level packaging method and packaging structure thereof

Abstract

The invention relates to a wafer-level packaging method and a packaging structure thereof. The packaging method comprises the following steps: providing a wafer which contains chip units; carrying out protrusion fabrication process on the front face of the wafer; forming a first groove between adjacent protrusions of the adjacent chip units on the front face of the wafer; filling coating materials in the first groove, wherein after the filling, the coating materials in the first groove are aligned with the surfaces of the chip units; forming a second groove in the back face of the wafer, wherein the depth of the second groove is equal to the difference between the thickness of the wafer and the thickness of the coating materials in the first groove; filling coating materials in the second groove, wherein after the filling, the height of the coating materials is higher than the back surface of the wafer; and carrying out simplified cutting. Through a wafer protrusion technology, wafer-level partial grooving and wafer-level coating material filling, high-density input / output ports of products and high reliability are achieved, the products are light, thin and short, productivity is high, and cost is low.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a wafer-level packaging method and a packaging structure thereof. Background technique [0002] With the development of semiconductor technology, the functions of semiconductor chips are becoming more and more powerful, resulting in the continuous increase of the signal transmission volume of semiconductor chips, and the requirements for high-density input and output ports of chip units are getting higher and higher. On the other hand, the development of information technology tends to be thinner and smaller, which not only requires reducing the size of the chip package, but also requires ensuring the high reliability and stability of the chip unit. [0003] Whether it is BGA (abbreviation for Ball Grid Array, Ball Grid Array) package or QFN (abbreviation for Quad Flat Non-leaded, square flat non-leaded) package, the traditional chip-level packaging has gradually failed to me...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the defects of low input and output port density, poor reliability, low production capacity, and large packaging volume existing in existing packaging products.

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