Storage control device, storage device, and control method for controlling storage control device

A storage control and storage block technology, which is applied in the direction of memory system, memory architecture access/allocation, memory address/allocation/relocation, etc., can solve the problems of small low-latency storage block and high capacity cost, and achieve the effect of increasing throughput

Inactive Publication Date: 2013-07-10
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the case of combining memory blocks with different access times, low-latency memory blocks usually have a smaller capacity than high-latency memory blocks, because low-latency memory blocks usually cost more per unit capacity than high-latency memory blocks

Method used

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  • Storage control device, storage device, and control method for controlling storage control device
  • Storage control device, storage device, and control method for controlling storage control device
  • Storage control device, storage device, and control method for controlling storage control device

Examples

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no. 1 example

[0041] [Typical Configuration of Information Processing System]

[0042] figure 1 is a block diagram showing a typical configuration of an information processing system of an embodiment of the present disclosure. This information handling system writes and reads data during information processing. This information processing system includes a host computer 100 and a data storage device 200 .

[0043] In information processing, the host computer 100 writes data to the data storage device 200 and reads written data from the data storage device 200 .

[0044] When writing data, the host computer 100 outputs a write command to the data storage device 20 via the signal line 109 together with the write data. The host computer 100 then receives a reply to the write command from the data storage device 200 via the signal line 109 . When reading data, the host computer 100 outputs a read command to the data storage device 200 via the signal line 109 . The host computer 100 then re...

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PUM

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Abstract

A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read.

Description

technical field [0001] The present disclosure relates to storage control devices. More specifically, the present disclosure relates to a storage control device that controls two memory blocks having different access times, a storage device, and a control method for controlling the storage control device. Background technique [0002] In the past, some storage devices combining two memory blocks with different access times constitute high-capacity storage devices with reduced access time (latency). For example, a flash memory is used as one storage block with a short access time (low latency), and a hard disk drive (HDD) is used as another storage block with a longer access time (high latency). In another example, NVRAM (Non-Volatile Random Access Memory) is used as a low-latency memory block, and Flash memory is used as a high-latency memory block. In the case of combining memory blocks with different access times, low-latency memory blocks generally have a smaller capacit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F12/02
CPCG06F12/0238G06F2212/7202G06F2212/7208G06F12/00
Inventor 大久保英明筒井敬一中西健一足立直大
Owner SONY CORP
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