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Apparatus and methods for mos transistors

A technology of transistors and main bodies, applied in the manufacture of transistors, semiconductor devices, semiconductor/solid-state devices, etc., can solve problems such as increased failure risk and short channel

Active Publication Date: 2017-03-01
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this shorter channel length may lead to short channel effects
More specifically, since the drain and source regions of the MOSFET are closer together, there may be an increased risk of punch-through failure

Method used

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  • Apparatus and methods for mos transistors
  • Apparatus and methods for mos transistors
  • Apparatus and methods for mos transistors

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Experimental program
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Embodiment Construction

[0038] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0039] The present disclosure will be described by way of embodiments in a specific context, namely, a lateral metal oxide semiconductor (MOS) device with stacked wells. However, embodiments of the present disclosure can be applied to various semiconductor devices.

[0040] figure 1A simplified cross-sectional view of a MOS transistor with a superimposed well is shown according to one embodiment. MOS transistor 100 includes a substrate 102 (preferably of P-type), a first P-type region 104 formed in the substrate 102 , and a second P-type region 106 . More specifically...

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PUM

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Abstract

The present invention involves a MOS transistor, which includes the first area of the first electrical substrate, the first electrical of the first electrical proportion, and the first electrical second area that forms in the first area., The first drainage / source area of the second -guided electrical characteristics in the second area, the second drain / source area of the second -guide electrical, and the main contact area of the first electrical character. Among themLooking down, the subject's contact area and the first drain / source area are formed by alternation.The invention also provides a device and method for MOS transistors.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more particularly, the present invention relates to a device and method for MOS transistors. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth due to the development of integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this development in integration density stems from the shrinking of semiconductor process nodes (for example, shrinking process nodes closer to the sub-20nm node). Semiconductor devices are being scaled down, requiring new technologies to maintain the performance of electronic components from one generation to the next. For example, low gate-drain capacitance and high breakdown voltage of transistors are desired for power applications. [0003] With the development of semiconductor technology, metal oxide semiconductor field effect transis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L27/088H01L29/06
CPCH01L27/088H01L27/092H01L29/7833H01L29/0638H01L21/761H01L29/66659H01L29/7835H01L29/0852H01L29/0623H01L29/0653H01L29/0696H01L29/1083H01L29/1095H01L29/7816
Inventor 周学良伍震威苏柏智柳瑞兴
Owner TAIWAN SEMICON MFG CO LTD