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Power device with bottom source electrode and preparation method

A technology of a power device and a bottom source is applied in the field of power devices with a bottom source and the preparation thereof, and can solve the problems of large substrate resistance, suppressing the scope of application of the packaging structure 24, and high cost.

Active Publication Date: 2014-01-29
ALPHA & OMEGA SEMICON INT LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the encapsulation structure 24 solves the problem of heat dissipation to a certain extent, it is expensive to manufacture such an object as the metal can-shaped structure 12 in actual production.
On the other hand, the positions of the source contact terminal 18 and the gate contact terminal are fixed, for example, the gate contact terminal cannot be adjusted to be in the same column as the raised edge 22, so it is difficult to fit the pad layout on the PCB. configuration, which undoubtedly inhibits the scope of application of the package structure 24
[0003] In addition, the substrate resistance of chips used in power devices is usually relatively large, which causes the on-state resistance RDson of the device to increase accordingly, so how to properly reduce the substrate resistance of the chip is a problem we need to solve

Method used

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  • Power device with bottom source electrode and preparation method
  • Power device with bottom source electrode and preparation method
  • Power device with bottom source electrode and preparation method

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Embodiment Construction

[0074] see Figure 2A and Figure 2B , respectively Figure 2C The schematic top view and the bottom bottom view of the power device 100A are shown, Figure 2C yes Figure 2B The enlarged cross-sectional view of the power device 100A along the dotted line AA in the vertical direction, Figure 2D-1 is a cross-sectional view along the dotted line BB. The power device 100A includes a metal base unit, and the metal base unit includes at least a first base 111 and a second base 112, a third base 113 and a second base 113 arranged around it and separated from it. The fourth base 114 (as Figure 2B ), they are basically the same thickness and lie in the same plane. Wherein, the first base 111 is generally a cuboid or a cube, and the third base 113 and the fourth base 114 arranged on both sides of the first base 111 extend longitudinally along the two longitudinal edges of the first base 111 respectively. , the second base 112 located near the first base 111 can be disposed at ...

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Abstract

The invention generally relates to a semiconductor power device and a preparation method thereof, or rather, aims to provide a power device with a bottom source electrode and a preparation method of the power device. The bottom source electrode of the power device is exposed from the bottom of a plastic package, the power device further comprises a metal electrode and an ultrathin chip, the metal electrode can be exposed from the top of the plastic package or not, and the resistance of a substrate is decreased by the aid of the ultrathin chip, so that the semiconductor power device has excellent electrical performance and heat dissipation performance.

Description

technical field [0001] The present invention generally relates to a semiconductor power device and a manufacturing method thereof, more precisely, the present invention aims to provide a power device with a bottom source and a manufacturing method thereof. Background technique [0002] We all know that the power consumption of power devices is generally very large. In applications similar to DC-DC power devices, based on the consideration of improving the electrical performance and heat dissipation performance of the device, it is usually a part of the metal electrodes of the device from the The plastic encapsulation material covering the chip is exposed in order to obtain the best heat dissipation effect. For example, in the US patent application US2003 / 0132531A1, a semiconductor package structure 24 that exposes the bottom electrode of the chip and is used to support the surface mount technology is shown, such as figure 1 As shown, a power chip MOSFET 10 is arranged in th...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/495H01L21/56H01L21/60
CPCH01L2924/13091H01L2224/40475H01L24/34H01L2224/73204H01L2224/16245H01L2224/40095H01L2924/181H01L2224/40245H01L2224/4007H01L2224/37011H01L2224/371H01L2224/37H01L2224/84345H01L2224/40H01L2224/84385H01L2224/32245H01L24/37H01L2924/00H01L2924/00012
Inventor 薛彦迅何约瑟哈姆扎·耶尔马兹鲁军石磊赵良黄平
Owner ALPHA & OMEGA SEMICON INT LP