A logic cell packing method for electronic design automation in fpga

A logic unit and electronic design technology, applied in the computer field, can solve problems such as ignoring the guarantee of circuit delay performance, long running time of FPGA development board circuits, etc., and achieve the effect of optimal delay, reduced quantity, and reduced running time

Active Publication Date: 2016-05-25
XIDIAN UNIV
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AI Technical Summary

Problems solved by technology

Although this method can fully control the number of configurable logic units CLB consumed by the final circuit while ensuring the continuous filling of the look-up table LUT, it ignores the guarantee of the final delay performance of the circuit, so that it is finally loaded on the FPGA development board. The circuit runs too long

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  • A logic cell packing method for electronic design automation in fpga
  • A logic cell packing method for electronic design automation in fpga
  • A logic cell packing method for electronic design automation in fpga

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Embodiment Construction

[0041] refer to figure 2 , the implementation steps of the present invention are as follows:

[0042]In step 1, the circuit after process mapping and unit division is set as a directed acyclic graph DAG.

[0043] Process mapping is to convert the circuit into a look-up table LUT integrated unit. If the size of the integrated unit exceeds the capacity of the FPGA, the look-up table LUT integrated unit must be divided into multiple LUT integrated units that can be placed in a given FPGA through unit division. Lookup table LUT unit group. Since the unit group is composed of multiple lookup tables LUTs connected to each other, the circuit can be regarded as a directed acyclic graph DAG, that is, the lookup table LUT with the logic function of the storage circuit is regarded as a directed acyclic graph in the circuit. A node in the graph, the line network connection between the lookup table LUT is regarded as an edge in a directed acyclic graph;

[0044] According to the connec...

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Abstract

The invention discloses a logical unit packing method for performing electronic design automation in an FPGA (Field Programmable Gate Array), mainly aiming to solve the problems of over big time delay of a circuit after packing and excessive consumption of configurable logical units (CLBs). A packing process comprises the following steps: representing a circuit which is subjected to process mapping and unit partition as a directed acyclic graph; initializing time delay information in the directed acyclic graph through a connecting way among look up tables (LUTs) in the circuit; computing the shatter value of each node through a breadth-first traversal method, and computing the criticality of each node in combination with the influence of each node on a key path of the circuit; computing the net gain value of each LUT according to the criticality of each node in combination with the number of nets of the LUTs and the number of nets used in the CLBs, and selectively filling the LUTs according to the net gain values. By adopting the logical unit packing method, the time delay of a final circuit is reduced greatly. Meanwhile, the number of the CLBs consumed in the final circuit is reduced greatly.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to an electronic design automation design boxing and packaging method, which can be used for the application design of various FPGA chips such as homogeneity and heterogeneity. Background technique [0002] In the mid-1980s, Xilinx Corporation of the United States first introduced the field programmable gate array device FPGA, which is a product of further development on the basis of the programmable logic array PLA and the general array logic GAL. With the rapid development of deep submicron manufacturing technology and design technology of integrated circuits, integrated circuits have entered the era of system-level SOCs. The million-gate Virtex series FPGA launched by Xilinx provides a new FPGA platform for solving system-level design problems. At present, the design technology and processing technology of foreign FPGA are mature, the product categories are complet...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G06F17/50
Inventor段振华李虎黄伯虎
OwnerXIDIAN UNIV