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Parallel processing of network packets

A packet processing and data packet technology, applied in the field of packet processors that manipulate data packets, can solve problems such as expensive routing resources and power consumption

Active Publication Date: 2014-06-11
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These methods are also more expensive in terms of routing resources and power consumption because a lot of redundant data is being sent to parallel pipelines

Method used

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  • Parallel processing of network packets
  • Parallel processing of network packets
  • Parallel processing of network packets

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Experimental program
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Embodiment Construction

[0033] One or more embodiments provide a hardware efficient parallel architecture for packet processing circuitry. The packet processing circuit includes a plurality of header extraction circuits for processing header information of a plurality of packets received on the data bus. The data bus is divided into multiple data lanes. Each header extraction circuit is configured to receive and extract header information from a respective subset of the data lanes. Because each extraction circuit only receives a subset of the lanes of data, less routing circuitry is required, and the extraction performed by each extraction circuit can be implemented using smaller shift circuits.

[0034] figure 1 An example packet processing pipeline 100 configured in accordance with one or more embodiments is shown. Interface circuit 124 receives and buffers words from N-byte data bus 102 in a pipeline of N-byte memory buffers. For each word received, the word is stored in a first memory buffer,...

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Abstract

A packet processing circuit includes a plurality of header extraction circuits (208-214), and a scheduling circuit (206) coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus (202) having a plurality of data lanes (302). In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request (304), and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes (306).

Description

technical field [0001] One or more embodiments of the invention relate generally to communication protocols, and more particularly to packet processors for manipulating data packets. Background technique [0002] As telecommunications line rates continue to increase, it is necessary to use wider and wider hardware data buses to maintain throughput. For example, in an FPGA implementation, a 512-bit data bus is typically used for 100Gb / s packet processing and a 2048-bit data bus is used for 400Gb / s packet processing. One consequence is that it is increasingly possible to include multiple packets in sets of bits across the data bus in parallel. As used herein, each set of bits transmitted in parallel over the full width of a data bus is referred to as a word. [0003] As an example, given a minimum packet size of 64 bytes, some packets may not fit entirely within a 512-bit word. A first data packet may begin in a previous word and end in a current word, and a second data pac...

Claims

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Application Information

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IPC IPC(8): H04L12/931H04L45/58
CPCH04L12/56
Inventor 高登·J·布农
Owner XILINX INC