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PMOS device leakage measurement method

A measurement method and device technology, applied in the direction of semiconductor/solid-state device testing/measurement, etc., can solve problems such as inaccurate test data and increased leakage current

Active Publication Date: 2016-11-30
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At this time, the leakage current IB measured at the body region contact region 60 will increase, resulting in inaccurate test data.

Method used

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  • PMOS device leakage measurement method

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Embodiment Construction

[0016] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0017] image 3 It schematically shows a leakage measurement structure of a PMOS device according to a preferred embodiment of the present invention.

[0018] like image 3 As shown, the PMOS device leakage measurement method according to a preferred embodiment of the present invention includes:

[0019] A wafer formed with a CMOS device is placed on a test tray 100, wherein the CMOS device includes a paired PMOS device and an NMOS device formed on the same substrate 10; and the PMOS device includes an N well formed in the substrate 10 20 in the P-type drain 40, P-type source 50 and N-type body contact region 60, the PMOS device also includes a gate 70 formed on the substrate 10; the NMOS device includes a P well formed in the substrate 10 N-...

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Abstract

A kind of PMOS device electric leakage measurement method, comprises: the wafer that will be formed with CMOS device is placed on the test tray, and wherein CMOS device comprises the paired PMOS device and NMOS device that are formed on the same substrate; And, PMOS device comprises the formation A P-type drain, a P-type source, and an N-type body contact region in an N-well in the substrate, and the NMOS device includes an N-type drain, an N-type source, and a P-type formed in a P-well in the substrate the N-type body contact region; the N-well is electrically isolated from the P-well by the isolation region; and a leakage measurement is performed on the PMOS device with the same voltage applied to the contact region of the NMOS device as on the N-type body contact region. The invention provides a PMOS device leakage measurement method, which can solve the situation that the PMOS off-state leakage occurs during the test without changing the layout of the existing CMOS device, improve the utilization efficiency of the device, and thereby reduce the layout Occupies an area to achieve the purpose of reducing costs.

Description

technical field [0001] The present invention relates to the WAT test (wafer acceptance test, wafer acceptability test) of CMOS semiconductor device, more specifically, the present invention relates to a kind of leakage measurement method of PMOS device. Background technique [0002] With the development of CMOS semiconductor device technology and the proportional size reduction, it is necessary to consider the power consumption of the system standby when designing, and it is necessary to reduce the off-state leakage of CMOS devices. Accurate measurement data is the foundation of process development. [0003] WAT (wafer acceptance test, wafer acceptability test) refers to testing the test key (test key) in the dicing line after the entire wafer is manufactured, but before packaging. The WAT test is an electrical test performed on various test structures on the semiconductor silicon wafer after completing all the manufacturing processes. Through the analysis of WAT data, pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
Inventor 杜宏亮
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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