jfet and its manufacturing method

Abstract

The invention discloses a JFET integrated in an LDMOS. A grid electrode region of the JFET is simultaneously used as a channel region of the LDMOS. The JFET and the LDMOS share a drift region and a drain region. A deep trap at the bottom part of the grid electrode region of the JFET forms a channel region of the JFET. A source region and the drain region of the JFET are respectively arranged at two sides of the channel region of the JFET. A source region of the JFET is formed on the surface of the deep trap. A second conductive type buried layer is formed at the position of a first conductively type deep trap at the bottom part of the channel region of the JFET and at the junction position of a second conductive type semiconductor substrate. The buried layer and the grid electrode region of the JFET realize the consumption of the channel region of the JFET together, and the fluctuation of the channel region consumption of the JFET, which is caused by the fluctuation of the doped concentration of the substrate when the substrate and the bottom part of the channel region of the JFET directly contact, is eliminated, so that the stability of the device is improved. The invention further discloses a manufacturing method of the JFET.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a junction field effect transistor (JFET). The invention also relates to a method for manufacturing a JFET. Background technique [0002] JFET uses the PN junction as the gate of the device to control the opening and closing of the channel. When the PN junction is negatively biased on the gate, both sides of the PN junction are depleted. When the channel is completely depleted, the device is in the pinch-off state of the channel. due. Otherwise, the device turns on. [0003] The ultra-high voltage junction field effect transistor needs the drain to withstand high voltage. Usually, the drift region of high-voltage LDMOS is used as the drift region of JFET to withstand high voltage, and the channel of high-voltage LDMOS is used as the gate of JFET. In this way, ultra-high voltage JFET can be produced, and the Share the photolithography plate with hig...

AI Technical Summary

Problems solved by technology

[0005] Ultra-high voltage JFETs all use ultra-high resistance substrates, and the doping concentration is very low, so that the resistivity of the substrate changes greatly, resulting in unstable performance of JFETs

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