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Silicon carbide semiconductor device and manufacturing method thereof

A semiconductor and silicon carbide technology, which is applied in the field of silicon carbide semiconductor devices and its manufacturing, can solve problems such as increased gate capacitance, delineated channel length, and difficult masks

Active Publication Date: 2019-05-17
SHINDENGEN ELECTRIC MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the third method requires two mask (Mask) processes to form the channel region, it is difficult to define the channel length with high precision due to mask alignment errors.
[0011] As a result, in the case of the third method, since it is necessary to set the channel length longer in consideration of mask alignment errors, the channel resistance and even the on-resistance as a component become variable. large, in addition, the gate capacitance will also become large

Method used

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  • Silicon carbide semiconductor device and manufacturing method thereof
  • Silicon carbide semiconductor device and manufacturing method thereof
  • Silicon carbide semiconductor device and manufacturing method thereof

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Experimental program
Comparison scheme
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Embodiment approach 1

[0058] 1. The silicon carbide semiconductor device according to the first embodiment

[0059] The silicon carbide semiconductor device 100 according to Embodiment 1 is the silicon carbide semiconductor device according to the first aspect of the present invention. The silicon carbide semiconductor device 100 according to Embodiment 1 is a power MOSFET.

[0060] Furthermore, in the following embodiments, the n-type is defined as n - , n, n + , n ++ in the order of p-type in accordance with p - , p, p ++ The order of indicates that the dopant concentration of the conductivity type becomes higher. These are approximations that represent relative magnitudes of dopant concentrations, such as n + type of region has a ratio n - Type area and n type area are higher, and than n ++ Type regions with low dopant concentration, but do not necessarily have a specific same dopant concentration.

[0061] The silicon carbide semiconductor device 100 related to Embodiment 1 is, for e...

Embodiment approach 2

[0108] The silicon carbide semiconductor device 102 according to Embodiment 2 is the silicon carbide semiconductor device according to the first aspect of the present invention. The silicon carbide semiconductor device 102 according to Embodiment 2 is a power MOSFET.

[0109] The silicon carbide semiconductor device 102 according to the second embodiment basically has the same configuration as the silicon carbide semiconductor device 100 according to the first embodiment, but the planar position of the end of the gate electrode is the same as that of the silicon carbide semiconductor device according to the first embodiment. 100 different. That is, in the silicon carbide semiconductor device 102 according to the second embodiment, as Figure 10 As shown, the end of the gate electrode 126 is located at n ++ type source region 120 .

[0110] In this way, although the silicon carbide semiconductor device 102 according to the second embodiment differs in the planar position of ...

Embodiment approach 3

[0116] The silicon carbide semiconductor device 104 according to the third embodiment is the silicon carbide semiconductor device according to the first aspect of the present invention. The silicon carbide semiconductor device 104 according to the third embodiment is a power MOSFET.

[0117] The silicon carbide semiconductor device 104 according to the third embodiment basically has the same configuration as the silicon carbide semiconductor device 100 according to the first embodiment, but the planar position of the end of the gate electrode is the same as that of the silicon carbide semiconductor device according to the first embodiment. 100 different. That is, in the silicon carbide semiconductor device 104 according to the third embodiment, as Figure 11 As shown, the end of the gate electrode 126 is located at n ++ The n-type source region 120 formed between the n-type semiconductor region 114 + type semiconductor region 134 . Furthermore, in the third embodiment, n ...

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Abstract

The silicon carbide semiconductor device 100 is characterized in that it includes: an n-type semiconductor region 114 formed on the n ‑ The surface of the type heteroepitaxial layer 112; the p-type body region 116 is formed at a deeper position than the n-type semiconductor region 114; p ‑ type channel region 118, is formed from n ‑ The surface side of the type heteroepitaxial layer reaches the p-type body region; and n ++ type source region 120, from n ‑ The surface of the type heteroepitaxial layer is formed laterally to the p-type body region, where p ‑ type channel region as well as n ++ type source region is formed as, p ‑ type channel region with n ++ An n-type semiconductor region remains between the type source regions, and the p ‑ Among the interfaces between the n-type channel region and the n-type semiconductor region, the interface on the outer peripheral side is located at a planar position inside the outer peripheral surface 116a of the p-type body region when viewed in plan. The channel region can be formed by a single mask process, and a sufficiently long channel length can be defined with high precision in a practical flow to the extent that the short channel effect does not occur.

Description

technical field [0001] The invention relates to a silicon carbide semiconductor device and a manufacturing method thereof. Background technique [0002] Figure 18 It is a cross-sectional view of a main part of a conventional silicon carbide semiconductor device 700 . [0003] A conventional silicon carbide semiconductor device 700 such as Figure 18 shown, including: n + Type low resistance silicon carbide substrate 710; n - Type heteroepitaxial (Heteroepitaxial) layer 712, formed in n + Type low-resistance silicon carbide substrate 710; p-type body (Body) region 716 is formed on the n - The surface of the epitaxial layer 712; the channel (Channel) region 718 is formed on the surface of the p-type body region 716; n ++ Type source (Source) region 720 and p ++ A body contact region 722 ; and a gate electrode 726 are formed at least on the channel region 718 via a gate insulating film 724 . also, Figure 18 Reference numeral 728 indicates an interlayer insulating film, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/12H01L29/739
CPCH01L21/0465H01L29/0696H01L29/086H01L29/1045H01L29/1095H01L29/1608H01L29/66068H01L29/7395H01L29/7802
Inventor 中村俊一菅井昭彦井上徹人
Owner SHINDENGEN ELECTRIC MFG CO LTD