Comparator offset voltage calibration circuit and method

Abstract

The invention discloses a comparator offset voltage calibration circuit and method. The method utilizes a state machine, a determination module and a calibration current generation module, and generates current according to the level signal at the offset voltage terminal of a comparator to offset a comparator offset voltage. The invention also discloses a majority voting device and method for improving comparator offset voltage calibration speed and accuracy. According to the invention, a comparator speed can not be reduced in calibration of a comparator offset voltage, and accurate calibration precision can be obtained; the comparator offset voltage calibration circuit and method can be suitable for a high speed SARADC circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a comparator offset voltage calibration circuit and method. Background technique [0002] In some applications of ADC, such as measuring instruments, there are certain requirements for the offset voltage of ADC (such as <0.5mV). At present, the common SARADC is mainly composed of comparator, charge distribution DAC and SAR logic. The comparator is the main analog circuit in SARADC. The error caused by the comparator is directly displayed at the input port of the ADC. For high-precision ADCs, the comparator generally uses a preamplifier plus a dynamic latch structure. Due to process deviations in the manufacturing process , so that the input equivalent offset voltage of the comparator is as high as several millivolts, which greatly limits the measurable accuracy of the ADC for the signal. [0003] The existing technology generally adopts two methods to offset the offset vol...

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Problems solved by technology

[0004] However, there are defects in the two existing methods of offsetting the offset voltage. Adding a capacitor at the output port of the latch will slow down the speed of the comparator. At the same time, this method is pre-calibrated, and the leakage of the capacitor will affect the accuracy of the offset voltage calibration of the comparator. ; In high-speed SARADC, since the input port of the comparator is directly connected to the output port of the DAC, the automatic zeroing technique is not applicable

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