Method and device for self-adaptive adjustment of chip memory write operation timing path

Abstract

The invention provides a self-adaption adjustment method and device for the write operation timing path of a chip storage. A write control storage unit outputs a write command and write data to a storage unit for reading operation, and the original write completion indication position is set to be valid one cycle after the write command. The storage unit outputs the original write completion indication position. The original write completion indication position is delayed by one cycle through one-stage delaying and delayed by two cycles through two-stage delaying so that a write completion indication position delayed by one cycle and a write completion indication position delayed by two cycles can be obtained. The access selection operation is conducted according to the judgment result of the work clock frequency, one path of three input paths including the original write completion indication position, the write completion indication position delayed by one cycle and the write completion indication position delayed by two cycles is selected as a write completion indication position, and therefore the write operation timing path is automatically adjusted according to the running frequency.

Description

technical field [0001] The invention relates to a method and device for self-adaptive adjustment of a chip memory write operation sequence path. Background technique [0002] With the development of SOC chip technology, users have higher and higher requirements for chip performance. Since the operating frequency of the chip directly affects the performance, the main frequency of the chip is getting higher and higher. At the same time, due to the complexity of the SRAM storage circuit, and in terms of function, it is required to complete the operation at the next clock beat when the command is received, so when the chip frequency increases rapidly, the writing speed of the SRAM obviously becomes the key to limit the chip frequency. path. The current timing path is from SRAM command collection to SRAM internal fetching and output to the SRAM port, and then to the unit that issued the command to complete the data sampling (especially when there are many modules mounted on the ...

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Problems solved by technology

At the same time, due to the complexity of the SRAM storage circuit, and in terms of function, it is required to complete the operation at the next clock beat when the command is received, so when the chip frequency increases rapidly, the writing speed of the SRAM obviously becomes the key to limit the chip frequency. path

The current timing path is from SRAM command collection to SRAM internal fetching and output to the SRAM port, and then to the unit that issued the command to complete the data sampling (especially when there are many modules mounted on the bus, the data path of the SRAM returning to the command initiator will be is very long and causes a large delay)

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