Array substrate, display panel and display device

Abstract

The invention discloses an array baseplate, a display panel and a display device. The array baseplate comprises a substrate, thin film transistors, grid lines and data lines, the grid lines and the data lines extend along a first direction and a second direction respectively and are crossed to limit multiple pixel units in one to one correspondence to the thin film transistors, each pixel unit comprises a first edge and a second edge respectively parallel to the first direction and the second direction, and length of each first edge is greater than that of the corresponding second edge; each pixel unit further comprises a pixel electrode, a grid electrode, a source electrode and a drain electrode of the thin film transistor are connected with the grid lines, the data lines and the pixel electrode respectively, and the source electrode, the drain electrode and the data lines are arranged on a same layer; the minimum distance between the drain electrode and the adjacent data line is a first distance, the maximum distance between the drain electrode and the adjacent grid line is a second distance, and the first distance is greater than or equal to the second distance. The array baseplate can realize high resolution while lower short-out risk between the drain electrode and the data lines.

Description

technical field [0001] The present invention relates to the display field, in particular to an array substrate, a display panel including the array substrate, and a display device including the display panel. Background technique [0002] With the rapid development of display technology, high-resolution and even ultra-high-resolution display screens have become an inevitable trend. However, as the resolution of displays increases, the pixels are packed closer together and each pixel becomes smaller and smaller. [0003] Please refer to figure 1 , figure 1 It is a top view of an array substrate in the prior art. The intersection of the data line 01 and the gate line 02 defines a plurality of pixels 03 , and each pixel 03 is respectively connected to a thin film transistor (not marked). Specifically, the source 04 of the TFT is electrically connected to the data line 01, the drain 05 of the TFT is electrically connected to the pixel electrode (not shown) in the pixel 03, a...

AI Technical Summary

Problems solved by technology

When the resolution of the display screen is higher, the size of the pixel 03 is smaller, so the distance between the drain 05 of the thin film transistor and the two adjacent data lines 01 or the two source 04 is getting smaller and smaller, and because the drain 05 It is set on the same layer as the data line 01 or the source 04, so there is a great short circuit risk between the drain 05 and the data line 01 or the source 04

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