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Memory structure and method for manufacturing the same

A manufacturing method and memory technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve problems such as difficult contact, improper coordination, and increased resistance

Active Publication Date: 2018-10-16
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

this can cause some problems
Smaller landing areas for connectors, for example, can lead to contact difficulties and mismatches, increasing associated electrical resistance

Method used

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  • Memory structure and method for manufacturing the same
  • Memory structure and method for manufacturing the same
  • Memory structure and method for manufacturing the same

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Embodiment Construction

[0052] Various embodiments will be described in more detail below in conjunction with the accompanying drawings. The attached drawings are for descriptive purposes only and not for limiting purposes. For clarity, some elements may be exaggerated or slightly displaced in some figures. Also, some elements and / or element numbers may be omitted from the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further recitation.

[0053] A memory structure according to an embodiment includes a substrate, stacks, storage layers, channel layers, and pad layers. The stack is disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stack includes a plurality of first stacks and a plurality of second stacks arranged alternately. Each of the stacks includes alternating stacks of conductive strips and insulating strips. A memory layer is partially dispose...

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Abstract

The invention discloses a memory structure and a method for manufacturing the same. A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channellayers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Description

technical field [0001] The invention relates to a semiconductor structure and a manufacturing method thereof. In particular, the present invention relates to a memory structure and method of manufacturing the same. Background technique [0002] Three-dimensional (3-D) semiconductor structures have been developed for reasons of volume reduction, weight reduction, increased power density, and improved portability, among other reasons. In addition, components and spaces in semiconductor structures continue to shrink. This can cause some problems. For example, smaller landing areas for connectors can lead to contact difficulties and mismatches, thereby increasing the associated electrical resistance. Accordingly, various improvements to semiconductor structures and methods of fabrication thereof remain desired. Contents of the invention [0003] The present invention relates to semiconductor structures and methods of fabrication thereof, and more particularly to memory str...

Claims

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Application Information

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IPC IPC(8): H01L27/11578
CPCH10B43/20H10B43/35H10B43/27
Inventor 赖二琨龙翔澜
Owner MACRONIX INT CO LTD
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