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Tristate gate circuit

A technology of tri-state gate circuits and NOT gates, which is applied to logic circuits with logic functions, etc., can solve problems such as unstable performance, affecting chip functions, and state errors

Inactive Publication Date: 2019-01-11
HANGZHOU KUANFU TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The three-state gate circuit in integrated circuits is a common circuit, and the instability of performance directly affects the function of the chip, and even state errors may occur

Method used

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  • Tristate gate circuit

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Embodiment Construction

[0008] The content of the present invention will be further described below in conjunction with the accompanying drawings.

[0009] Three-state gate circuits, such as figure 1 As shown, it includes the first inverter 10, the first NAND gate 20, the second inverter 30, the third inverter 40, the second NAND gate 50, the fourth inverter 60, the first NMOS transistor 70 and the second NMOS tube 80:

[0010] The input terminal of the first inverter 10 is connected to the input terminal A, and the output terminal is connected to an input terminal of the first NAND gate 20 and an input terminal of the second NAND gate 50; the first NAND gate An input terminal of the NOT gate 20 is connected to the input terminal of the first inverter 10 and an input terminal of the second NAND gate 50, the other input terminal is connected to the input terminal B, and the output terminal is connected to the second inverter. The input terminal of the phaser 30; the input terminal of the second inve...

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Abstract

The present invention discloses a tristate gate circuit. The tristate gate circuit comprises a first inverter, a first NAND gate, a second inverter, a third inverter, a second NAND gate, a four inverter, a first NMOS tube and a second NMOS tube. The tristate gate circuit allows the output state to be more stable.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to tri-state gate circuits. Background technique [0002] The three-state gate circuit in integrated circuits is a common circuit, and the instability of performance directly affects the function of the chip, and even state errors may occur. In order to make the output state more stable, a tri-state gate circuit to prevent errors is designed. Contents of the invention [0003] The invention aims to solve the deficiencies of the prior art and provide a tri-state gate circuit with higher stability. [0004] Three-state gate circuit, including the first inverter, the first NAND gate, the second inverter, the third inverter, the second NAND gate, the fourth inverter, the first NMOS transistor and the second NMOS Tube: [0005] The input terminal of the first inverter is connected to the input terminal A, and the output terminal is connected to an input terminal of the f...

Claims

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Application Information

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IPC IPC(8): H03K19/20
CPCH03K19/20
Inventor 孟庆生
Owner HANGZHOU KUANFU TECH