Three-dimensional network topology structure and routing algorithm thereof

A topology and three-dimensional network technology, applied in the computer field, can solve problems such as low utilization of escape channels, no solution proposed, increase system cost, etc., and achieve low cost, low power consumption, and reduce system cost and power consumption.

Active Publication Date: 2019-04-02
中科曙光信息产业成都有限公司 +1
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Adding virtual channels to build virtual subnets can effectively avoid deadlocks by separating traffic, but the disadvantage of this method is that it requires more resources, which will greatly increase system costs for ultra-large-scale networks with high-dimensional topologies
The escape virtual channel can also avoid deadlocks. When congestion occurs, data packets enter the escape virtual channel route, which can resolve congestion. The disadvantage is that the utilization rate of the escape channel is relatively low.
[0013] For the above-mentioned problems in related technologies, no effective solution has been proposed yet

Method used

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  • Three-dimensional network topology structure and routing algorithm thereof
  • Three-dimensional network topology structure and routing algorithm thereof
  • Three-dimensional network topology structure and routing algorithm thereof

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Embodiment Construction

[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art fall within the protection scope of the present invention.

[0047] The present invention provides a three-dimensional network topology structure, including: a plurality of first-layer virtual subnets, and each first-layer virtual subnet is a Torus topology structure. Among them, multiple first-layer virtual subnets form a full interconnection topology structure through TSV interconnection links, and the full interconnection topology is a second layer virtual subnet.

[0048] The above-mentioned technical scheme of the pres...

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Abstract

The invention discloses a three-dimensional network topology structure and a routing algorithm thereof. The three-dimensional network topology structure comprises multiple first-layer virtual subnets,wherein each first-layer virtual subnet is a Torus topology structure; the multiple first-layer virtual subnets form a full-interconnection topology structure through a TSV interconnecting link, andthe full-interconnection topology is a second-layer virtual subnet. The technical scheme of the invention constructs a hierarchical network topology structure through combining the Torus topologies and the full-interconnection topology based on a three-dimensional integration technology and a TSV technology, which at least can effectively compress the network diameter and reduce the communicationdelay.

Description

Technical field [0001] The present invention relates to the field of computer technology, in particular to a three-dimensional network topology structure and its routing algorithm. Background technique [0002] With the rapid development of semiconductor device technology, the feature size of large-scale integrated circuits is getting smaller and smaller, and the number of transistors in the integrated circuit inside the chip is increasing. The number of cores integrated by the processor is also increasing. In order to connect these processor cores and work together, a communication network dedicated to the internal interconnection of the chip is proposed, that is, the Network-on-Chip (NoC). Network-on-chip refers to a multi-processor system based on network communication implemented on a single chip. Multi-core processors require special restrictions on resources and power consumption to have simple wiring, fewer interconnections, lower latency, lower power consumption, and hi...

Claims

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Application Information

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IPC IPC(8): H04L12/933H04L12/931H04L12/947
CPCH04L49/109H04L49/15H04L49/25H04L49/70
Inventor 苏勇万伟李斌
Owner 中科曙光信息产业成都有限公司
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