SM3 algorithm round iteration system and iteration method based on coarse-grained reconfigurable architecture

Abstract

The invention discloses an SM3 algorithm round iteration system and iteration method based on a coarse-grained reconfigurable architecture. The iteration system includes a system bus, a reconfigurable processor and a microprocessor. The reconfigurable processor includes a configuration unit, an input advanced Output register group, output first-in-first-out register group, general-purpose register file and 4 reconfigurable array blocks. The first-out register group is connected to the microprocessor through the system bus; the four reconfigurable array blocks are respectively connected to the input / output first-in first-out register group and the general register file; the four reconfigurable array blocks are connected through the general register file Data storage, reading and transmission; the output first-in-first-out register group is connected with the microprocessor through the system bus. While supporting a certain degree of flexibility, this technical solution realizes the efficient operation of the SM3 algorithm by improving the parallelism of the DES algorithm and optimizing the pipeline.

Description

technical field [0001] The invention belongs to the field of embedded reconfigurable systems, and in particular relates to a large-scale coarse-grained embedded reconfigurable system and a processing method thereof applied in the fields of communication and encryption. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream methods in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is...

AI Technical Summary

Problems solved by technology

However, the interconnection of these arrays is relatively simple, and a large number of bit shifts and more rounds are required in the iterative operation of the SM3 algorithm, so the efficiency and speed of the operation are low

Traditional reconfigurable computing systems have big problems in SM3 computing efficiency and computing cycle

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