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A SHA256 implementation method and system based on large-scale coarse-grained reconfigurable processor

A processor and coarse-grained technology, applied in the architecture with a single central processing unit, electrical digital data processing, instruments, etc., can solve the problems of low computing efficiency and speed, and achieve increased computing parallelism, improved computing efficiency, and reduced The effect of the operation cycle

Active Publication Date: 2018-08-21
SOUTHEAST UNIV
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Problems solved by technology

However, the interconnection of these arrays is relatively simple, and the operation of the SHA256 method requires a large amount of intermediate data storage and a large number of rounds, so the efficiency and speed of the operation are low
Traditional reconfigurable computing systems have big problems in terms of computing efficiency and computing cycles of SHA256

Method used

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  • A SHA256 implementation method and system based on large-scale coarse-grained reconfigurable processor
  • A SHA256 implementation method and system based on large-scale coarse-grained reconfigurable processor
  • A SHA256 implementation method and system based on large-scale coarse-grained reconfigurable processor

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Embodiment Construction

[0033] The present invention will be further described below in conjunction with the accompanying drawings.

[0034] figure 1 It is a structural block diagram based on a large-scale coarse-grained reconfigurable processor, which includes 10 reconfigurable array blocks, 1 general-purpose register file, 1 input FIFO register bank and 1 output FIFO register bank. Data transfers between the reconfigurable processor and the bus interface are buffered by a first-in first-out register bank. The general register file is used for data communication and data cache between reconfigurable array blocks.

[0035] The reconfigurable array block further includes 4 reconfigurable array operation rows, a general register file read port operation row selector and a general register file write port operation row selector. Through a general-purpose register read port operation line selector, you can choose to read the data of the general-purpose register file from the specified reconfigurable ar...

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Abstract

The invention discloses an SHA256 realizing method and system based on a large-scale coarse-grain reconfigurable processor. The system comprises a first-in first-out register set, a general register file, an arithmetic logic unit, a bit permutation network, a byte permutation network, a data loading unit and a data output unit. Aiming at an SHA256 method, by means of multiple times of iteration, optimization and acceleration are carried out in the reconfigurable processor in a partial expansion and middle result data caching mode.

Description

technical field [0001] The invention designs the field of embedded reconfigurable systems, especially a large-scale coarse-grained embedded reconfigurable system and its processing method applied in the fields of communication and encryption. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream methods in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is very poor. [0004] In or...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/7867
Inventor 曹鹏陈圣华杨锦江陆启乐刘波
Owner SOUTHEAST UNIV
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