A device for accelerating convolution and pooling operations based on reconfigurable technology

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a device for accelerating convolution and pooling operations based on reconfigurable technology. The device of the present invention includes: a reconfigurable computing unit, a convolution weight storage module, a feature value storage module, and a control module; After product operation, maximum pooling operation, or average pooling operation, the result is written back to the feature value storage module. The invention overcomes the technical problem that a plurality of different components are required to separately process the convolution and pooling operations in the prior art computing device for convolution and pooling operations, saves circuit area and power consumption, and improves system energy efficiency.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a device for convolution and pooling operations in a deep neural network algorithm. Background technique [0002] Today, deep neural network algorithms show amazing potential in fields such as computer vision and natural language processing. In order to improve the computing energy efficiency of deep neural network algorithms, technicians have developed a series of deep neural network algorithm acceleration chips. [0003] The deep convolutional neural network algorithm is currently one of the most widely used deep neural network algorithms. It is generally composed of convolutional layers, pooling layers and other layers of different operations connected. Among them, the pooling operation is divided into two different operations: maximum pooling and average pooling. In the current existing architecture, in order to deal with pooling operations, there ar...

AI Technical Summary

Problems solved by technology

The first is to use general-purpose processing units such as CPUs to calculate pooling operations, but the parallelism of processing pooling operations by general-purpose processing units such as CPUs is low, and data transmission between convolution acceleration modules and general-purpose processing units such as CPUs takes up A large amount of bus bandwidth, which in turn affects bus data transmission such as weights

The second is to use multiple operation acceleration modules with different structures to accelerate different operations separately, which will waste chip area and power consumption

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