Multiplier, data processing method and chip

Abstract

The invention provides a multiplier, a data processing method and a chip. The multiplier comprises a correction Booth encoding circuit, a correction Wallace tree circuit and a correction accumulationcircuit, the output end of the correction Booth encoding circuit is connected with the input end of the correction Wallace tree circuit, and the output end of the correction Wallace tree circuit is connected with the input end of the correction accumulation circuit. The multiplier can carry out multiplication operation on various data with different bit widths, and the universality of the multiplier is improved.

Description

technical field

[0001] The present application relates to the field of computer technology, in particular to a multiplier, a data processing method and a chip. Background technique

[0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm.

[0003] Generally, existing multipliers using different bit widths can implement multiplication operations for data with different bit widths. However, for low-bit-width data operations, existing multipliers that can handle high-bit-width data cannot be used to perform multiplication operations, resulting in low versatility of the multiplier. Contents of the invention

[0004] Based on t...

Examples

Embodiment Construction

[0068] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0069] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 and figure 2 shown.

[0070] Such as figure 1 Shown is a structural diagram of a multiplier provided by an embodiment. Such as figure 1 As shown, the multiplier includes: a modified Booth encoding circuit 11, a modified Wallace tree circuit 12 and a modified accumulation circuit 13, the modifie...

technical field

[0001] The present application relates to the field of computer technology, in particular to a multiplier, a data processing method and a chip. Background technique

[0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm.

[0003] Generally, existing multipliers using different bit widths can implement multiplication operations for data with different bit widths. However, for low-bit-width data operations, existing multipliers that can handle high-bit-width data cannot be used to perform multiplication operations, resulting in low versatility of the multiplier. Contents of the invention

[0004] Based on t...

Examples

Embodiment Construction

[0068] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0069] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 and figure 2 shown.

[0070] Such as figure 1 Shown is a structural diagram of a multiplier provided by an embodiment. Such as figure 1 As shown, the multiplier includes: a modified Booth encoding circuit 11, a modified Wallace tree circuit 12 and a modified accumulation circuit 13, the modifie...

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