Analog-digital converter capable of offsetting sampling noise

Abstract

The invention discloses an analog-to-digital converter capable of offsetting sampling noise. The analog-to-digital converter comprises a sampling circuit used for collecting analog input signals; a sampling noise canceling circuit whose input end is connected with the output end of the sampling circuit and which is used for canceling noise generated by the sampling circuit; a comparator whose input end is connected with the output end of the sampling canceling circuit and output end is connected with the input end of a logic circuit, and which is used for comparing output signals of the sampling noise canceling circuit and outputting a comparison result to the logic circuit; and the logic circuit whose output end of is connected with the sampling circuit and which is used for outputting adigital output signal, processing the comparison result to obtain a control signal and controlling the output voltage of the sampling circuit according to the control signal. The analog-to-digital converter can counteract noise introduced by sampling operation, so that a very small sam`pling capacitor can be adopted in the ADC without causing loss of a signal-to-noise ratio, and the power consumption, the area and the design complexity of a driving circuit are reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to an analog-to-digital converter capable of canceling sampling noise. Background technique [0002] An Analog-to-Digital Converter (ADC) is an electronic device that converts an analog signal in the real world into a digital signal in an electronic system. Successive Approximation Register (SAR) ADC is a low-power ADC structure, which has a wide range of applications in the Internet of Things, wearable devices, implantable medical electronics and other fields. [0003] In an electronic system, the input signal of SAR ADC is provided by the input driver of its previous stage, and the reference signal required for SAR ADC conversion is provided by the reference buffer of its previous stage, such as figure 1 shown. The input driver and the reference buffer constitute the driving circuit of the SAR ADC, and the load of the driving circuit is the sampling capacitor i...

AI Technical Summary

Problems solved by technology

However, increasing the capacitance of the sampling capacitor will bring a lot of cost to the circuit design

The sampling capacitor is the load of the pre-stage driving circuit. A large sampling capacitor brings a great burden to the ADC driving circuit. In order to drive a large sampling capacitor, it is necessary to increase the power consumption, area and design complexity of the driving circuit to improve its driving ability

Images