Hierarchical structure focused on high performance SRAM (Static Random Access Memory)

Abstract

The invention relates to a hierarchical structure focused on a high performance SRAM (Static Random Access Memory). Word lines adopt classification technology, a trigger is inserted between a global word line GWLL and a local word line, a memory array is divided into N levels in which the number is the same as that of Bit cells, the GWLL is classified into M lines through a word line encoder module, the number of Bit cells in one line is T, namely, the number of Bit cells in each level is T / N, and the modules after classification are structurally the same; after the binary SRAM address data is coded through the word line encoder module, the selected GWLL is lifted; when the rising edge of the next clock arrives, the internal trigger of the selected line triggers simultaneously, and the Bit cells of the N modules in the line are all opened; in write operation, the specific written position of the Bit cell is decided after the coding of a column selector module; in read operation, the specific position of Bit cell finally serving as the output also depends on the coding result of the column selector module, and the selected Bit cell data is output through bit lines and the column selector.

Description

technical field [0001] The invention relates to a method for internal optimal grading of a high-performance SRAM and its architecture. The invention can effectively realize that the total delays of the first stage and the second stage on the critical path of the SRAM are approximately equal, and avoid the problem of short delay boards. In addition, compared with the traditional architecture, the internal word line hierarchical architecture greatly reduces the requirements for the driving capability of the flip-flop, and also reduces the delay, so as to realize the optimization of SRAM performance. Background technique [0002] SRAM (Static Random Access Memory) is a volatile memory (lost after power-off, and the data after power-on again is random data). It uses a bistable circuit as a storage unit, which can save the data stored in it without refreshing the circuit, and has a fast working speed, so it is a device that directly exchanges data with the CPU in a computer syst...

AI Technical Summary

Problems solved by technology

The Cache in most Intel processors adopts multi-cycle read and write, which increases the clock speed, but the actual throughput does not increase

This is because multiple cycles of reading and writing are equivalent to controlling the SRAM after clock frequency division, and there is no change in the throughput of the SRAM.

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