Multiplier, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problem of high power consumption, and achieve the effect of reducing area and power consumption

Active Publication Date: 2020-06-09
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in some small numerical calculation scenarios, the existin

Method used

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  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment

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Embodiment Construction

[0073] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0074] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 shown.

[0075] Such as figure 1 Shown is a structural diagram of a multiplier provided by an embodiment. Such as figure 1 As shown, the multiplier includes: an improved encoding circuit 11, an improved Wallace tree circuit 12 and an accumulation circuit 13; the output of the improved encoding ci...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: an improved coding circuit, an improved Wallace tree group circuit and an accumulation circuit, the output end of the improved coding circuit is connected with the input end of the improved Wallace tree group circuit, the output end of the improved Wallace tree group circuit isconnected with the input end of the accumulation circuit, the multiplier can carry out multiplication operation on various data with different bit widths, and the area of an AI chip occupied by the multiplier is effectively reduced; and, in addition, the multiplier performs accumulation operation on the partial product of the target code by improving a Wallace tree group circuit, and the power consumption of the multiplier can be effectively reduced.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, various types of artificial intelligence (AI) chips have become the focus of the current technology industry and society. As one of the main circuits of the AI ​​chip, the performance of the multiplier circuit is particularly important. [0003] At present, the Wallace tree compression circuit is a very important unit in the multiplier, and the power consumption of the Wallace tree compression circuit directly affects the power consumption of the multiplier. When realizing the multiplication operation, the multiplier uses the existing Wallace tree compression circuit to compress the partial product, and uses a group of full adders to accumulate the compressed results and output the target result. Wherein, the ...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06N3/06
CPCG06F9/30007G06N3/06Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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