Word line decoding circuit, word line gating method, memory and electronic equipment
A decoding circuit and word line decoding technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as difficulty in applying large-scale storage arrays, and achieve the effect of realizing the input data bit width
Active Publication Date: 2022-02-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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But without the word line decoding circuit, this method of directly controlling the word line is difficult to apply to large-scale memory arrays
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[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0027] It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0028] In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indic...
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The invention discloses a word line decoding circuit, a word line gating method, memory and electronic equipment, relates to the field of memory, and solves the problem of in-memory calculation applied to large-scale storage arrays. The word line decoding circuit includes: a previous stage decoding circuit and a subsequent stage decoding circuit; the previous stage decoding circuit includes a first decoder and a second decoder, and the latter stage decoding circuit includes a word line selection circuit and a gate device. Each first decoder is electrically connected to the word line selection circuit, and the output end of each second decoder is electrically connected to the input end of the corresponding strobe; the output end of each strobe is electrically connected to the word line selection circuit. connect. In the storage mode, the word line decoding circuit gates the word lines in the storage area; in the in-memory computing mode, the word line decoding circuit gates the word lines in the in-memory computing area. The word line decoding circuit provided by the present invention is used for applying in-memory calculation to large-scale memory arrays.
Description
technical field [0001] The invention relates to the technical field of memory, in particular to a word line decoding circuit, a word line gating method, memory and electronic equipment. Background technique [0002] With the development of the semiconductor industry and the difference in demand, the performance gap between the processor and the memory is getting bigger and bigger, and the memory access speed cannot keep up with the data processing speed of the processor. This kind of memory bottleneck that seriously hinders the performance of the processor is named "memory wall". In-memory computing is the technical path proposed to solve this problem. The working principle is to select multiple word lines in the memory array for parallel data transmission. , completing the calculation of the analog domain of the data inside the memory array, so as to improve the speed of the calculation in the memory. [0003] In an in-memory computing circuit, direct input of address data...
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IPC IPC(8): G11C16/08
CPCG11C16/08
Inventor 窦春萌叶望王琳方王雪红刘璟刘琦吕杭炳刘明
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI