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Comprehensive CPU model

A model and type of technology, applied in the field of logic function verification, can solve problems such as large time cost and labor cost, and achieve the effects of reducing development cycle, simple structure, and reducing complexity

Pending Publication Date: 2021-10-12
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if you only verify the logic functions outside the CPU, this will bring huge time and labor costs

Method used

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  • Comprehensive CPU model

Examples

Experimental program
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Embodiment 1

[0032] This embodiment discloses a comprehensive CPU model, such as figure 1 As shown, this CPU model mounts n bus interfaces, n is a positive integer greater than 1, and n can be configured according to system requirements.

[0033] The CPU model includes an instruction acquisition module, an instruction analysis module, a data comparison module, an interface arbitration routing module and a bus protocol generation module.

[0034] The instruction obtaining module is used to obtain the instructions required for model operation, and provide the instructions to the instruction parsing module;

[0035] The instruction parsing module realizes parsing the compiled instruction into a binary that can be recognized by the CPU to achieve the purpose of distinguishing the instruction function, and then passes the parsed instruction to the data comparison module;

[0036] The data comparison module compares the result of executing the instruction with the received instruction, so as to...

Embodiment 2

[0041] In this example, if figure 2 As shown, the instruction acquisition module is an instruction storage module, that is, the instruction is acquired by means of embedded instruction storage, and the acquired instruction is passed to the instruction analysis module.

Embodiment 3

[0043] Such as image 3 As shown, the instruction acquisition module in this embodiment is an instruction reading module, that is, the instruction is obtained by reading instructions from an external storage, and the obtained instructions are passed to the instruction analysis module.

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PUM

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Abstract

The invention discloses a Comprehensive CPU model; the CPU model is provided with a plurality of bus interfaces, and each bus interface has own ID. The CPU model comprises an instruction acquisition module, an instruction analysis module, a data comparison module, an interface arbitration routing module and a bus protocol generation module. The instruction acquisition module is used for acquiring an instruction required by model operation and providing the instruction to the instruction analysis module; the instruction analysis module parses the compiled instruction into a binary system which can be identified by a CPU so as to achieve the purpose of distinguishing an instruction function, and then transmits the parsed instruction to the data comparison module; the data comparison module is used for comparing an instruction execution result with the received instruction so as to judge whether the instruction is correctly executed or not; the interface arbitration routing module determines a sending bus port according to the content of the instruction; and the bus protocol generation module sends the received instruction or data to a bus interface according to a bus protocol format.

Description

technical field [0001] The invention relates to a synthesizable CPU model, which is used for logic function verification between the CPU and the bus. Background technique [0002] With the continuous development of integrated circuits, the scale of system design is getting larger and larger, and the division of modules is becoming more and more complicated. As the core CPU for scheduling system work, it is becoming more and more important. Generally, the CPU is an important part of the system, and the authorized IP is mostly used, and the flexibility and convenience of use are limited. In the entire ASIC design process, it is necessary to configure CPU parameters in the early stage, integrate the CPU into the system, and perform RTL simulation. In the later stage, it is necessary to perform FPGA synthesis and board debugging. After a series of behaviors, the entire system can be scheduled through the CPU to observe whether the behavior of the entire system meets expectation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3308
CPCG06F30/3308
Inventor 师开伟孙中琳
Owner SHANDONG SINOCHIP SEMICON
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