PAD multiplexing circuit, MCU and control method

Abstract

The invention discloses a PAD multiplexing circuit, an MCU and a control method. The PAD multiplexing circuit comprises an ADC, an ADC gating switch, a pull-down enabling transistor, a first switch, a second switch, a third switch and an IO pin. The IO pin is connected with a drain electrode of a first output driving transistor and a drain electrode of a second output driving transistor of the general input / output interface; the second end of the ADC gating switch is connected with the IO pin; the source electrode of the pull-down enabling transistor is grounded, and the drain electrode is connected with the first end of the ADC gating switch; the first switch is connected with the input port of the ADC and the ADC gating switch; the second switch is connected with a power supply pin of the universal input / output interface and a positive reference voltage port of the ADC; and the third switch is connected with a positive reference voltage port of the ADC, a power port of the ADC and an analog power pin. According to the invention, an RTP IO PAD and an ADC acquisition simulation IO PAD can be saved, and the total area of a chip is indirectly reduced.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a PAD multiplexing circuit, an MCU and a control method. Background technique [0002] A microcontroller (MCU) is a very large-scale integrated circuit (VLSI) that integrates a central processing unit (CPU), memory, digital-to-analog converter (ADC) and peripheral interfaces on a single chip. In order to meet different application combinations, MCU usually has rich peripheral interfaces, such as audio and video interfaces, touch screen interfaces, Ethernet interfaces, signal acquisition interfaces, etc., and these interfaces will occupy a lot of pin resources. [0003] On the other hand, with the miniaturization of semiconductor manufacturing technology, the critical dimension has reached 7nm and below, the logic core circuit area in the chip is greatly reduced, but the area of ​​the peripheral input / output circuit (IO PAD) cannot be reduced proportionally. This is a common ...

Images