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Parallel processing method and device of graph assembly line and readable storage medium

A parallel processing and graphics processor technology, applied in machine execution devices, processor architecture/configuration, multi-programming devices, etc., can solve problems such as reduced rendering efficiency and performance bottlenecks, and achieve the effect of improving processing efficiency

Active Publication Date: 2022-05-10
摩尔线程智能科技(北京)有限责任公司
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Problems solved by technology

However, since the generation of the polygon list needs to be strictly in accordance with the order of the input primitives, and the operation of different cores is completely independent, the graphics processor of the TBR architecture usually performs all the geometric phase operations by a single core, thus Lead to performance bottlenecks and reduced rendering efficiency

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  • Parallel processing method and device of graph assembly line and readable storage medium
  • Parallel processing method and device of graph assembly line and readable storage medium
  • Parallel processing method and device of graph assembly line and readable storage medium

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Embodiment Construction

[0034] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0035] In the description of the embodiments of the present application, it should be understood that terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, acts, components, parts or combinations thereof disclosed in the specification, and do not It is intended to exclude the possibility of the existence of one or more other features, figures, steps, acts, parts, parts or comb...

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Abstract

The invention provides a parallel processing method and device for a graphics pipeline and a readable storage medium, the method is applied to a driving layer of a multi-core graphics processor, the graphics pipeline adopts a TBR-based architecture, and the method comprises the following steps: receiving a plurality of drawing call instructions, grouping the plurality of drawing call instructions to generate a specified number of geometric stage requests, each geometric stage request carries a sequence identifier determined according to an original input sequence of a plurality of drawing call instructions; in response to the rendering instruction, distributing a specified number of processing requests to a plurality of cores of the multi-core graphics processor in parallel, and enabling the plurality of cores to execute geometric phase operations in parallel to generate a polygon list corresponding to each geometric phase request; and splicing the polygon list according to the sequence identifier carried by each geometric stage request to obtain a target polygon list. By means of the method, the geometric stage processing efficiency based on block rendering can be improved.

Description

technical field [0001] The invention belongs to the field of graphics processing, and in particular relates to a parallel processing method, device and computer-readable storage medium of a graphics pipeline. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] Graphics processing technology can be divided into immediate mode rendering (Immediate Mode Rendering, referred to as IMR) and tile-based rendering (Tile-based Rendering, referred to as TBR). In IMR, rendering is performed immediately whenever a primitive of object data is generated in the geometry stage. , in TBR, divides the frame into virtual tiles to perform rendering on each tile. In these modes, TBR reduces memory bandwidth and reduces power consumption. Therefore, TBR is frequently used in mobile devices where powe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/20G06F9/38G06F9/50
CPCG06T1/20G06F9/3885G06F9/505Y02D10/00
Inventor 焦韬
Owner 摩尔线程智能科技(北京)有限责任公司
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