Digital logic correction circuit for a pipeline analog to digital (A/D) converter

Abstract

A digital logic correction (DLC) circuit (68) for a pipeline analog to digital (A / D) converter (60). The A / D converter (60) having a plurality of stages, each stage producing at least a pair of digital output bits from which a digital representation of an analog input signal can be obtained. The DLC circuit (68) has an adder (176), the adder (176) having a plurality of inputs and an output. The DLC circuit (68) has a plurality of digital delay sets, each digital delay set comprising at least one digital delay (170), an input (172) of the digital delay set receiving a corresponding digital output bit and an output (174) of the delay set providing a delayed digital output bit to a respective adder input. The DLC circuit (68) has a clock generator (70), the clock generator (70) providing clock signals to the DLC circuit (68) to synchronize the arrival of the output of each digital delay set at the adder inputs during a data-valid-period. A primary clock signal is applied to the digital delay sets for every other stage. A secondary clock signal is applied to the remaining digital delay sets. The timing of the primary and secondary clock signals being effective to delay the digital output bits of each stage via the respective digital delay sets to cause the digital output bits to arrive at the adder inputs during the data-valid-period so that the adder (176) produces the digital representation of the analog input signal at the adder output.

Description

technical field [0001] Broadly speaking, the present invention relates to pipeline analog-to-digital (A / D) converters, and more particularly to digital logic modification circuits for pipeline analog-to-digital (A / D) converters, i.e. reducing internal shift register (shift register) number of digital logic correction circuits. Background technique [0002] For analog-to-digital (A / D) converters, there is always a need for an analog-to-digital converter that can accurately convert an analog voltage signal into a corresponding digital representation. There is also a need for A / D converters that are faster, consume less power, and occupy a smaller area on an integrated circuit chip. [0003] FIG. 1 shows a conventional pipeline analog-to-digital (A / D) converter 10 . The A / D converter 10 converts an analog electronic input signal (V IN ) into a digital representation of the analog signal (D OUT ). The example shown is a 4-bit A / D converter, but it will be appreciated that i...

AI Technical Summary

Problems solved by technology

Therefore, in one timing cycle, the digital data output of each cascaded stage of A / D converter 10 will be delayed twice

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