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Semiconductor apparatus and its making method

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as inability to seek withstand voltage, increased short channel effect, and failure to seek working withstand voltage

Inactive Publication Date: 2006-06-07
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

⑥The injected electrons reach the drain region 57, which further causes avalanche multiplication
[0015] In addition, in order to improve the operating withstand voltage (VSUS), such as Figure 9 As shown in , it is also considered to increase the amount of ion implantation and increase the concentration of the N-type drain region, but as shown by the white circle in the figure, it is not possible to achieve a sufficient improvement in withstand voltage
Furthermore, conversely due to Figure 13 The concentration of the end portion A of the N-type drain region 56 shown in FIG. Large, and the increase of the snap back (rapid return) phenomenon caused by the increase of the peak value of the substrate current (I Sub), and the drop of the source-drain voltage (BVDS), so far, there has not been a work-resistant Effective method for improvement of pressure

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  • Semiconductor apparatus and its making method
  • Semiconductor apparatus and its making method
  • Semiconductor apparatus and its making method

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Embodiment Construction

[0072] Hereinafter, embodiments of the semiconductor device and its manufacturing method according to the present invention will be described with reference to the drawings.

[0073] exist Figure 4 Among them, in the semiconductor device of the first embodiment of the present invention, the first gate insulating film 4 and the second gate insulating film 6 are formed on a semiconductor substrate (P-Sub) 1 of one conductivity type, for example, P-type, A gate electrode 7 is formed across the second gate insulating film 6 from the gate insulating film 4 . Moreover, a high-concentration reverse-conduction (N+) type source region 9 is formed so as to be adjacent to one end of the gate electrode 7, and a first lower channel region opposite to the above-mentioned source region 9 is formed through the channel region under the gate electrode 7. Concentration of the reverse conduction (N) type drain region 5A, connected to the first low concentration of the reverse conduction N type ...

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Abstract

The object of the present invention is to improve the working withstand voltage. It is characterized in that it has: an N+ type source region (9), adjacent to one end of the gate electrode (7); an N-type drain region (5A) and an N-type drain region (5B) formed in connection with the drain region (5A) ), under the above-mentioned first gate insulating film (4), there is an impurity concentration peak at least at a position of a predetermined depth in the above-mentioned substrate, and the impurity concentration becomes lower in a region close to the substrate surface; the N+ type drain region (10 ), separated from the other end of the above-mentioned gate electrode (7) and included in the above-mentioned N-type drain region (5B): and the N-type layer (11), from one end of the above-mentioned first gate insulating film (4) across the above-mentioned N+ type drain region (10).

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method. More specifically, it relates to a technique for improving the operating withstand voltage characteristics of a high withstand voltage MOS transistor for high power supply voltage (HV-VDD) used in an LCD driver, an EL driver, etc. . Background technique [0002] Hereinafter, regarding semiconductor devices related to conventional examples, while referring to Figure 13 The cross-sectional view of the LDD type high withstand voltage MOS transistor shown in . [0003] exist Figure 13 In this case, a gate electrode 53 is formed on a P-type semiconductor substrate (P-Sub) 51 via a gate insulating film 52 . Moreover, an N+ type source region 54 is formed so as to be adjacent to one end of the above-mentioned gate electrode 53, an N-type drain region 56 is formed opposite to the above-mentioned source region 54 via a channel region 55, and an N+ type drain region 57 is al...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L21/265
CPCH01L21/26586H01L29/66659H01L29/7835H01L29/42368H01L29/0847H01L29/78
Inventor 菊地修一西部荣次铃木琢也
Owner SANYO ELECTRIC CO LTD